今日,正交分頻多工(OFDM)技術被廣泛的使用於通訊系統之中,而這種技術對於同步有著敏感性的問題.同步的錯誤包含了時間軸與頻域部分,這些同步的誤差將導致符際干擾(ISI)與載波間干擾(ICI). 為了解決這些問題,每個符號(Symbol)的時間估測及同步以及載波頻率誤差的補償成為了重要的課題.在本篇論文中將對這些同步的問題與以討論,並針對於AWGN以及Fading channel作效能分析.除此之外,該架構使用FPGA驗證功能狀況,並記錄於本篇論文中.
除了上述的問題外,於OFDM的通訊系統中FFT的速度與效能往往是系統裡的重要考量.在這些相關的系統裡,耗電量將會是主要考量,本篇論文提出一個使用記憶體為基準的重複運算架構的FFT,用以運用低功耗無線都會型區域網路(WiMax)的基頻傳送與接收設計中,該架構使用 Radix-8的Butterfly架構,也因此其耗電量相對於Radix-4 Butterfly架構可以大幅減少百分之二十八.本篇論文提出的FFT架構主要有三個優點,第一:較少的Butterfly來回運算可減低耗電量.第二:使用管線化設計的Radix-8 Butterfly可以很容易的提昇其運算頻率.第三:均分為兩等份的記憶體使用方法可使記憶體的使用效能達到最高
本篇論文使用Altera Stratix II FPGA 將以上的兩大部分,同步與FFT串聯設計於FPGA中最驗證.

Today, there are many communication system uses orthogonal frequency division multiplexing (OFDM) and the most important things is its sensitivity to synchronization problems. The synchronization errors are included time and frequency parts and they will due to inter symbol interference (ISI) and inter carrier interference (ICI). For these reasons, symbol timing synchronization and carrier frequency offset compensation are the key functions .In this thesis, these functions are discussed in AWGN channel and fading channels on implemented architecture. The architecture is implemented on FPGA and reports in this thesis.
Besides these problems, the FFT processor is the most speed critical part in the OFDM communication systems. In these systems, low power is usually one of the major concerns. We propose a memory based recursive FFT design in FPGA for the low power base-band OFDM transmitter and receiver for WiMax (Wireless Metropolitan Area Network) application. It is implemented by radix-8 FFT. As results, the power consumption will be reduced by 28% compared to radix-4 FFT [2]. The proposed architecture has three advantages: (1) fewer butterfly iterations to reduce power consumption, (2) pipeline of radix-8 butterfly to speed up clock frequency, (3) even distribution of memory access to make the best utilization efficiency of SRAM ports.

[1] IEEE Std 802.16™-2004 (Revision of IEEE Std 802.16-2001), “IEEE Standard for Local and metropolitan area networks”, 3 Park Avenue, New York, NY 10016-5997, USA
[2] Sang-Chul Moon and Ln-Cheol Park ”Area-Efficient Memory-Based Architecture for FFT Processing” IEEE International Symposium on Circuits and Systems, 25-28 May 2003,pp101-104
[3] GUOAN BI and E. V. JONES “A Pipelined FFT Processor for Word-Sequential Data” IEEE transactions on Acoustics. Speech ,Signal Processing, vol. 37pp.1982-1985
[4] Chao-Kai Chang; Chung-Ping Hung; Sau-Gee Chen;” An efficient memory-based FFT architecture” IEEE International Symposium on Circuits and Systems, 25-28 May 2003 pp.129 -132
[5] Ching-Hsien Chang; Chin-Liang Wang; Yu-Tai Chang;” A novel memory-based FFT processor for DMT/OFDM applications” IEEE International Conference on Acoustics, Speech, and Signal, 15-19 March 1999, pp.1921 – 1924
[6] Chin-Liang Wang, Ching-Hsien Chang, “A new memory-based FFT processor for VDSL transceivers” IEEE Int. Symp. On Circuits and Systems, vol. 4, pp.670-673, May 2001.
[7] M. Hasan, T. Arslan and J.S. Thompson “A Novel Coefficient Ordering based Low Power Pipelined Radix-4 FFT Processor for Wireless LAN Applications” IEEE transactions on consumer electronics, Vol. 49, No. 1, FEBRUARY. 2003
[8] Alan V. Oppenheim, Ronald W.schafer with John R. Buck,”Discrete-time signal processing second edition”
[9] Y. H. Hu. Cordic-based vlsi architectures for digital signal processing. In IEEE Signal Processing Mag., pages 16-35, 1992.
[10] Haviland G. L., and Tuszynski, A. A., “A CORDIC Arithmetic Processor Chip,” IEEE Trans. On Computer, Vol. C-29, No. 2, pp. 4-45, February, 1980.
[11] J. Terry, and J. Heiskala, OFDM Wireless LANs: A Theoretical and Practical Guide, SAMS Publishing, 2001.
[12] J-J. van de Beek, M. Sandell, P. O. Börjesson, "ML Estimation of Time and Frequency Offset in OFDM
systems," IEEE Transactions on Signal Processing, Vol. 45, No. 7, July 1997
[13] Meng-Han Hsieh and Che-Ho Wei, "A Low-Complexity Frame Synchronization and Frequency Offset Compensation Scheme for OFDM Systems over Fading Channels," IEEE Transactions on Vehicular Technology, Vol. 48, No. 5, September 1999
[14] P. H. Moose, "A Technique for Orthogonal Frequency Division Multiplexing Frequency Offset Correction," IEEE Transactions on Communications, Vol. 42, No. 10, October 1994
[15] T. Pollet, M. van Bladel, M. Moeneclaey, "BER Sensitivity of OFDM Systems to Carrier Frequency Offset and Wiener Phase Noise," IEEE Transactions on Communications, Vol. 43, Issue 2, Part 3, February, March,
April 1995, pp. 191–193
[16] T. Pollet, P. Spruyt, M. Moeneclaey, "The BER Performance of OFDM Systems using Non-Synchronized Sampling," IEEE Global Telecommunications Conference 1994, pp. 253–257
[17] T. M. Schmidl, D. C. Cox, "Low-Overhead, Low-Complexity [Burst] Synchronization for OFDM," IEEE International Conference on Communications, Vol. 3., 1996, pp 1301–1306