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研究生: 鄭家慧
Cheng, Chia-Hui
論文名稱: 垂直型超接面功率金氧半場效電晶體研究
Study On Advanced Power MOSFETs: Vertical Superjunction MOSFET
指導教授: 黃智方
Huang, Chih-Fang
口試委員: 黃宗義
龔正
李坤彥
吳添立
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 114
中文關鍵詞: 垂直型超接面功率金氧半場效電晶體
外文關鍵詞: Vertical, Superjunction, Power MOSFET
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  • 本文研究並提出了一種先進的垂直雙擴散金屬氧化物半導體(VDMOS)功率電晶體。本文使用二維元件模擬評估了VDMOS元件漂移區中Superjunction的使用。Sentaurus中的所有相關物理模型均設置為初始模型並且啟用。從製程模擬中獲得VDMOS元件中相當重要的Superjunction結構的摻雜濃度分佈,並利用量測結果來進行檢驗。本文研究且討論了與Superjunction VDMOS結構在截止狀態崩潰電壓(BV)下的性能以及與特定的導通電阻有關的關鍵的設計參數,以及由雪崩能量EAS定義的非箝位電感負載切換(UIS)能力和元件失效時間。通過調整VDMOS元件漂移區中的Superjunction結構區的磊晶的厚度,可以將導通電阻降低35%,同時保持與基準的Superjunction VDMOS相同的BV。此外,提出了一種新型的深接面終端區,並將其與常規的Floating Guard Ring Termination進行了比較。所提出的結構中的終端區寬度減小了63%,同時保持了相同的崩潰電壓,並使用與常規的元件相同的製程步驟展現了出色的初步高溫反向偏壓(HTRB)可靠性。使用Mixed-mode模擬並通過將主動區Cell和終端區並聯,搭配適當的面積因子,對不同電荷平衡條件下的Superjunction VDMOS的失效進行了數值研究。


    An advanced vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied and is presented in this dissertation. The use of a superjunction in the drift region of a VDMOS device has been evaluated using two-dimensional device simulation. All relevant physical models in Sentaurus are set to default and are enabled. The important doping profiles in the superjunction the VDMOS device are obtained from the process simulation and checked using measurement. Key design parameters related to the performance of the superjunction VDMOS structure in OFF-state breakdown voltage (BV) ,and the specific ON-resistance are examined and discussed, as well as the unclamped inductive load switching (UIS) capability defined based on the avalanche energy EAS and the failure time. By adjusting the thickness of the superjunction epitaxy layer in the drift region of the VDMOS device, the ON-resistance is reduced by 35%, while maintaining the same BV as compared to that of the baseline superjunction VDMOS structure. In addition, a novel deep junction termination method is proposed and compared with the conventional floating guard ring termination. The termination width in the proposed structure is reduced by 63%, while maintaining the same blocking voltage and exhibiting excellent preliminary high temperature reverse bias (HTRB) reliability using the same process steps as a conventional device. The failure of the superjunction VDMOS structure under different charge balance conditions has been numerically studied using mixed-mode simulation and by paralleling the active area cell and the termination with the appropriate area factors.

    摘要1 Abstract 2 Acknowledgements.3 CHAPTER 1 Background.5 1.1 Motivation5 1.2 Dissertation Outline 8 1.3 References 8 CHAPTER 2: Principles and Process for a Superjunction 11 2.1 Fundamentals of a Power MOSFET 11 2.2 Motivation 14 2.3 Superjunction Concept 15 2.4 The Superjunction Process 17 2.4.1 Trench-Refill Technology 18 2.4.2 Multi-epi technology 19 2.5 References 21 CHAPTER 3: Active Area Study 24 3.1 Analysis of the Active Area 24 3.2 Key Design Parameters for the Structure of the Active Area 25 3.3 Comparison between the Simulation and the Experiment for the Active Area 27 3.3.1 Comparison of Device Structures28 3.3.2 DC Performance 35 3.4 Optimization of Ron,sp 38 3.4.1 Literature Review 38 3.4.2 Quantitative Analysis related to the Compensation Effect for the Process Parameters 39 3.4.3 Reducing the WSJ and the N-bottom Pinch-off Effect 42 3.5 Discussion of Simulation Results 44 3.5.1 Effects of the WSJ and the Implant Dose 44 3.5.2 Effects of Thermal Annealing Time46 3.5.3 Effects of the Epitaxial Layer Thickness.49 3.6 Quasi-Fermi Potential and Ron,sp 51 3.7 Measurement Results after Optimizing the Simulation 56 3.8 References 60 CHAPTER 4: Edge Termination Study 61 4.1. Introduction 61 4.2 Basic Structures Analysis 62 4.3 Device Structure 63 4.4 Simulation Results and Analysis 66 4.5 Electrical Characteristics of Fabricated Device 72 4.6 References 75 CHAPTER 5: UIS Test and the Reliability of the Proposed Structure 77 5.1 Introduction 77 5.1.1 Principles of the UIS Test 77 5.1.2 Motivation 80 5.2 Literature Review of the UIS Test 84 5.2.1 BJT Turn-on 84 5.2.2 Intrinsic Doping Concentration 86 5.2.3 Charge Balance for the Superjunction.87 5.2.4 Failures in Edge Termination.92 5.3 Simulation Results and Analysis 98 5.3.1 Mixed-Mode Method 98 5.3.2 OFF-State for the Device based on Various Dosages 99 5.3.3 Active Area -> Termination 100 5.3.4. Termination -> Active Area 102 5.3.5 Active Area -> Termination -> Active Area 103 5.3.6 Summary of the Simulation Results 104 5.4 Experiment Results 105 5.5 Reliability Test 108 5.6 References 110 CHAPTER 6 Conclusions 113 6.1. Conclusions 113 6.2. Future work 114

    [1-1] A. Villamor Baliarda, “Avalanche Ruggedness of Local Charge Balance Power Super Junction Transistors,” PhD. Dissertation, Universitat Autònoma de Barcelona, 2013.
    [1-2] L. Lorenz, G. Deboy, A. Knapp, M. Marz, “COOLMOS/sup TM/-a new milestone in high voltage power MOS”, Proc. 11th Int. Symp. Power Semiconductor Devices and ICs, pp. 3-10, 1999.
    [1-3] D. J. Coe, “High voltage semiconductor devices,” European Patent 0053854, Jun. 16, 1982.
    [1-4] S. Shirota, S. Kaneda, “New type of varactor diode consisting of multi-layer p-n junctions”, J. Appl. Phys., vol. 49, no. 12, pp. 6012-6019, Dec. 1978.
    [1-5] F. Udrea, G. Deboy and T. Fujihira, “Superjunction Power Devices, History, Development, and Future Prospects,” in IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 713-727, March 2017.
    [1-6] K.-H. Oh et al., “Experimental investigation of 650V superjunction IGBTs,” in Proc. 20th Int. Symp. Power Semiconductor Device ICs, 2008, pp. 299–302.
    [1-7] M. Saggio, D. Fagone, S. Musumeci, “Mdmesh: Innovative technology for high voltage power MOSFETs”, IEEE Int. Symp. Power Semiconductor Devices and ICs, pp. 65-68, 2000.
    [1-8] R. Eden, “The world market for power semiconductor discretes & modules 2016.” Power Semiconductor Forecast Report, Information Handling Services (IHS) Technology, 2016. [Online]. Available: https://technology.ihs.com/580305/power-semiconductor-forecastreport-2016.
    [1-9] D. R. Disney, A. K. Paul, M. Darwish, R. Basecki, and V. Rumennik, “A new 800 V lateral MOSFET with dual conduction paths,” in Proc. 13th Int. Symp. Power Semiconductor Device ICs, pp. 399-402, 2001.
    [1-10] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. 12th Int. Symp. Power Semiconductor Device ICs, pp. 12-18, 2000.
    [1-11] F. Udrea, “Semiconductor Device,” U.S. Patent 6 111 289, Apr. 12, 1999.
    [1-12] F. Udrea, A. Popescu, and W. I. Milne, “3D RESURF double-gate MOSFET: A revolutionary power device concept,” Electron. Lett., vol. 34, no. 8, pp. 808–809, Apr. 1998.
    [1-13] F. Udrea, A. Popescu, and W. Milne, “The 3D RESURF junction,” in Proc. 10th Int. Symp. Power Semiconductor Device ICs, pp. 141-144, 1998.
    [1-14] T. Fujihira, “Theory of semiconductor superjunction devices,” Jpn. J. Appl. Phys., vol. 36, no. 10, pp. 6254-6262, Oct. 1997.
    [2-1] John L. B. Walker. Handbook of RF and Microwave Power Amplifiers, UK: Cambridge University Press, 2012.
    [2-2] Alpha and Omega Semiconductor, Appl. Note MOS-007 pp.1-10.
    [2-3] Somsubhra Ghosh, “Low voltage power MOSFET - A Discussion,” Dec. 25, 2015. [Online]. Available: https://www.slideshare.net/somghosh1/low-voltage-power-mosfet-a-discussion.
    [2-4] MathWorks, “N-Channel LDMOS FET,” 2016. [Online]. Available: https://www.mathworks.com/help/physmod/sps/ref/nchannelldmosfet.html.
    [2-5] R. Mendoza Macias. “Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device.” M.A. thesis, University of Central Florida, Orlando, 2016.
    [2-6] Phenitec Semiconductor, “LDMOS as a power semiconductor device (1),” Technical Report, Feb. 28 2018.
    [2-7] S. S. V. Gupta, Shivani Saxena. “A Review on VDMOS as a Power MOSFET.” IOSR-JECE, pp.119-124, 2016.
    [2-8] B. Baliga, Fundamentals of Power Semiconductor Devices, New York:Springer Verlag, 2008.
    [2-9] Xing-Bi Chen and J. K. O. Sin, “Optimization of the specific on-resistance of the COOLMOS/sup TM/”, IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 344-348, Feb. 2001.
    [2-10] Xing-Bi Chen and J. K. O. Sin, “Correction to "Optimization of the specific on-resistance of the COOLMOS/sup TM/",” in IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1288-1288, June 2001.
    [2-11] W Choi, D Son, M Hallenberger, “New generation Super-Junction MOSFET for lower switching noise and reliable operation by controlled dv/dt and di/dt switching behavior,” In PCIM Europe, 2013.
    [2-12] Praveen M. Shenoy, Anup Bhalla, Gary M. Dolny. “Analysis of the Effect of Charge Imbalance on the Static and Dynamic Characteristics ofthe Super Junction MOSFET[C],” ISPSD, pp.99-102, 1999.
    [2-13] P. N. Kondekar, Hawn Sool Oh, Young-Bum Cho and Young-Beom Kim, “The effect of static charge imbalance on the on state behavior of the superjunction power MOSFET: CoolMOS,” The Fifth International Conference on Power Electronics and Drive Systems, 2003. PEDS 2003., Singapore, 2003, pp. 77-80 Vol.1.
    [2-14] P. N. Kondekar, “Static off state and conduction state charge imbalance in the superjunction power MOSFET,” TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region, Bangalore, pp. 1455-1459 Vol.4, 2003.
    [2-15] P. N. Kondekar, "Effect of static charge imbalance on forward blocking voltage of superjunction power MOSFET," 2004 IEEE Region 10 Conference TENCON 2004., pp. 209-212 Vol. 4, 2004.
    [2-16] Stmicroelectronics S.R.L., “Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure”, US6300171, 1998.
    [2-17] Toshiba Corporation, “SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME,” US 7714385, 2005.
    [2-18] Toshiba Corporation, “Semiconductor device,” US7358566, 2005.
    [2-19] E. S. Jung, S. S. Kyoung, E. G. Kang, “Design and fabrication of super junction MOSFET based on trench filling and bottom implantation process,” J. Elect. Eng. Technol., vol. 9, no. 3, pp. 964-969, 2014.
    [2-20] Stmicroelectronics S.R.L., “Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure,” US 6300171, 1998.
    [3-1] B. Baliga, Fundamentals of Power Semiconductor Devices, New York: Springer Verlag, 2008.
    [3-2] MA-TEK, [Online]. Available:
    http://www.ma-tek.com/zh-tw/services/overview.
    [3-3] W. Saito, "Process design of superjunction MOSFETs for high drain current capability and low on-resistance", Proc. IEEE Power Semiconductor Devices ICs, pp. 475-478, May 2017.
    [3-4] D. Disney, G. Dolny, “JFET Depletion in SuperJunction Devices,” 2008 20th International Symposium on Power Semiconductor Devices and IC's, pp. 157-160, 2008.
    [4-1] L. Lorenz, G. Deboy, A. Knapp and M. Miirz, “COOLMOSTM- a New Milestone in High Voltage Power MOS,” IEEE Power Semiconductor Devices and ICs, pp. 3-10, 1999.
    [4-2] Xing-Bi Chen and J. K. O. Sin, “Optimization of the specific on-resistance of the COOLMOS/sup TM/”, IEEE Trans. Electron Devices, vol. 48, no. 2, pp. 344-348, Feb. 2001.
    [4-3] W. Saito, I. Omura, S. Aida, S. Koduki, M. Izumisawa, H. Yoshioka, H. Okumura, M. Yamaguchi and T. Ogura, “A 15.5mΩcm2-680V Superjunction MOSFET Reduced On-Resistance by Lateral Pitch Narrowing,” IEEE Power Semiconductor Devices and ICs, pp. 1-4, 2006.
    [4-4] N. Reinelta, M. Schmittb, A. Willmerothb, H. Kapelsb, and G. Wachutkaa., “Increasing the Breakdown Capability of Superjunction Power MOSFETs at the Edge of the Active Region,” 13th European Conf. on Power Electronics and Applications, 2009.
    [4-5] T. Yamaguchi, H. Okumura, T. Shiraishi, T. Fujita, Y. Ata, and K. Kobayashi, “High Aspect Ratio Deep Trench Termination (HARDT2) Technique Surrounding Die Edge as Dielectric Wall to Improve High Voltage Device Area Efficiency,” IEEE Power Semiconductor Devices and ICs, pp. 479-482, 2017.
    [4-6] Y. Bai, A. Q. Huang and X. Li, “Junction termination technique for super junction devices,” 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), Toulouse, France, 2000, pp. 257-261.
    [4-7] R. Stengl and U. Gosele, “Variation of Lateral Doping - A New Concept to Avoid High Voltage Breakdown of Planar Junctions,” Int. Electron Devices Meeting, pp. 154-157, 1985.
    [4-8] S. Hardikar, R. Tadikonda, D. Green, K. Vershinin, and E. Narayanan, “Realizing High-Voltage Junction Isolated LDMOS Transistors With Variation in Lateral Doping,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2223-2228, 2004.
    [4-9] Y. Liang, G. Samudra and C. Huang, Power Microelectronics: Device and Process Technologies 2nd Ed., Singapore: World Scientific, pp. 66, 2017.
    [4-10] R. Stengl and U. Gosele, “Variation of lateral doping - A new concept to avoid high voltage breakdown of planar junctions,” 1985 International Electron Devices Meeting, Washington, DC, USA, 1985, pp. 154-157.
    [4-11] Chia-Hui Cheng, Chih-Fang Huang, Kung-Yen Lee, Feng Zhao, “A Novel Deep Junction Edge Termination for Superjunction MOSFETs,” Electron Device Letters IEEE, vol. 39, no. 4, pp. 544-547, 2018.
    [4-12] Chia-Hui Cheng, Chih-Fang Huang, Kung-Yen Lee, Feng Zhao, “A Novel Deep Junction Edge Termination for Superjunction MOSFETs,” International Conference on Solid State Devices and Materials (SSDM), 2017.
    [5-1] Renesas Electronics Corporation, Appl. Note 1968, pp.1-6.
    [5-2] Infineon, “600V Cool MOS™ C7 Design Guide,” Appl. Note, pp.1-28.
    [5-3] Infineon Technologies, Appl. Note ,1005, pp.1-17.
    [5-4] M. Ren, Z. H. Li, G. M. Deng, L. X. Zhang, M. Zhang, X. L. Liu, J. X. Xie, B. Zhang, “A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching,” Chin. Phys. B, 21 (4): 048502, 2012.
    [5-5] L. Jiang, W. Lixin, L. Shuojin, W. Xuesheng, H. Zhengsheng, “Avalanche behavior of power MOSFETs under different temperature conditions,” Journal of Semiconductors, vol. 32, pp. 014001, 2011.
    [5-6] R. R. Stoltenburg, “Boundary of power-MOSFET, unclamped inductive-switching (UIS), avalanche-current capability,” Proceedings, Fourth Annual IEEE Applied Power Electronics Conference and Exposition, pp. 359-364, 1989.
    [5-7] W. Saito et al., “A 20mΩcm2 600 V-class Superjunction MOSFET,” In Proc. ISPSD, pp. 459–462, 2004.
    [5-8] A. Villamor Baliarda et al., “Influence of charge balance on the robustness of trench-based super junction diodes,” Microelectron. Rel., vol. 52, no. 9–10, pp. 2409-2413, 2012.
    [5-9] G. Deboy et al., “Power Semiconductor compensation structure and method for producing the same,” US Patent No. 7646061 B2(2010).
    [5-10] S. Sridevan, “Superjunciton device with improved ruggedness,” US Patent No. 7,166,890 B2, 2007.
    [5-11] M. Ren et al., “Super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device with optimized avalanche breakdown current path,” CN 102832245A, 2011.
    [5-12] A. Villamor Baliarda, “Avalanche Ruggedness of Local Charge Balance Power Super Junction Transistors,” PhD. Dissertation, Universitat Autònoma de Barcelona, 2013.
    [5-13] P. N. Kondekar, C. D. Parikh and M. B. Patil, “Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer,” Power Electronics Specialists Conference. Proceedings, pp. 1769-1775, 2002.
    [5-14] G. A. M. Hurkx and N. Koper, “A physics-based model for the avalanche ruggedness of power diodes,” In Proc. ISPSD, pp. 169-172, 1999.
    [5-15] S. Kim, K. Oh, Y. Kim and C. Yun, “Degradation of avalanche ruggedness of power diodes by thermally induced local breakdown, ” 2006 37th IEEE Power Electronics Specialists Conference, Jeju, 2006, pp. 1-5.
    [5-16] S. Soneda et al., “Analysis of a drain-voltage oscillation of MOSFET under high dV/dt UIS condition, ” 2012 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, 2012, pp. 153-156.
    [5-17] Chia-Hui Cheng, Chih-Fang Huang, Kung-Yen Lee, Feng Zhao, “A Novel Deep Junction Edge Termination for Superjunction MOSFETs,” Electron Device Letters IEEE, vol. 39, no. 4, pp. 544-547, 2018.

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