隨著積體電路製程進步到深次微米的時代，光罩製作的成本可達到一、兩百萬美金之多。多重設計專案晶圓(MPW)可以將不同的設計放在同一組光罩裡，進而降低整體製造的成本。然而，因為晶片設計複雜度的不同，每個設計都有其所需要的製程(technology process)，例如某一個設計需要一層複晶(poly)及四層的金屬層(metal layers)，而某個較複雜的設計可能需要更多層的金屬層。而且，不同製程的設計無法從同一片晶圓(wafer)中切割生產出來，但是它們可以放在同一組光罩中來降低整體製造的成本。在本篇論文中，我們提出一個以線性規劃為基礎的(ILP-based)的佈局器(floorplanner)來解決光罩佈局(reticle floorplan)的問題。同時，我們也提出以模擬退火為基礎(SA-based)且能考量到圓形晶圓的晶圓切割法。由實驗的結果可觀察出我們的方法比之前所提出的佈局器平均而言能節省約28%的成本

As the VLSI manufacturing technology advances into the deep sub-micron (DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which puts different dies onto the same set of masks is a good cost-sharing approach. Every design needs to be produced by its desired technology process, such as 1 poly with 4 metal layers (1P4M), or 1 poly with 5 metal layers (1P5M). Dies with different desired manufacturing processes cannot be produced from the same wafer, but they can be put onto the same set of masks in order to reduce the total cost of used masks and wafers. In this thesis, we propose a novel integer linear programming (ILP)-based floorplanner for shuttle runs consisting of projects requiring different desired processes. A simulated annealing-based side-to-side wafer dicing planner which takes into account the circular shape of the wafer is also presented. This problem formulation was not considered and discussed before. Experimental results show that our approach achieves 28% wafer reduction on average compared to a previous simulated annealing-based reticle floorplanner.

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