一個高能源效率十二位元每秒取樣一億次之時間交錯連續漸進式類比數位轉換器使用共用半休眠切換技術

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研究生：	林宜玄 Lin, Yi-Hsuan
論文名稱：	一個高能源效率十二位元每秒取樣一億次之時間交錯連續漸進式類比數位轉換器使用共用半休眠切換技術 An Energy-Efficient 12b 100MS/s Time-Interleaved SAR ADC Using Shared Semi-Resting Switching Technique
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	洪浩喬 Hong, Hao-Chiao 邱進峯 Chiu, Chin-Fong 陳柏宏 Chen, Po-Hung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	108
中文關鍵詞：	高速、低電壓、高能源效率、時間交錯式、連續漸進式類比數位轉換器
外文關鍵詞：	high-speed, low-voltage, energy-efficient, time-interleaved, SAR ADC
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本論文提出一個使用共用半休眠切換技術以求高能源效率的12位元、每秒取樣1億次之時間交錯連續漸近式類比數位轉換器。
在物聯網應用當中，連網裝置通常以低電壓操作有較佳的能源效率表現也有較長的電池續航力，因此本論文之類比數位比較器設計在一個0.5伏與1伏雙供電之系統。低電壓循序漸近類比數位轉換器之轉換速率非常低，為了達到每秒取樣一億次的取樣速率，採用時間交錯式的系統架構。當中的子轉換器延續半休眠切換之概念，以求較低的電容切換功耗。本論文改良半休眠切換應用於時間交錯式架構，提出共用半休眠切換技術，透過重複使用閒置的子轉換器，降低所需之子轉換器總數。
本電路之原型晶片採用40奈米1P9M互補式金氧半導體製程製作，核心電路面積為600×870 μm2。在1.0/0.5 V供電以及每秒取樣1000萬次操作之下，本晶片可達到56.145 dB之訊號雜訊加失真比(SNDR)，對應等效解析度(ENOB)為9.03位元。其功耗為35 μW，換算能源效率指標(Walden figure-of-merit, FoMW)為9.36 fJ/conversion-step。在取樣頻率為每秒取樣1億次時，僅達到46.121 dB之SNDR，ENOB為7.369位元，其功耗為284 μW，能源效率指標FoM為17.28 fJ/conversion-step。

This thesis presents a 12-bit 100MS/s time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) using shared semi-resting (SSR) switching technique.
For Internet-of-Things (IoT) applications, the connecting devices usually operate in low voltage supply for better energy efficiency and longer lifetime of batteries. Thus, the proposed ADC is designed in a dual supply system of 0.5 V and 1 V. The conversion rate of a low-voltage SAR ADC is slow. To achieve targeted 100MS/s sampling rate, the ADC adopts time-interleaved architecture. The sub-ADCs inherit the low capacitor switching power concept of the semi-resting (SR) switching technique. This thesis proposes the shared semi-resting (SSR) switching technique, which is a reformed SR technique used in TI architecture. The total required number of sub-ADCs is reduced by re-using idle sub-ADCs.
The prototype was fabricated in 40 nm 1P9M CMOS technology with a core area of 600×870 μm2. At 1.0/0.5 V supply voltage and 10 MS/s sampling rate, the ADC achieves SNDR 56.145 dB with corresponding ENOB 9.03-bit and consumes a power of 0.035 mW, resulting in a Walden figure-of-merit (FoMW) 6.69 fJ/conversion-step. At 100 MS/s sampling rate, the ADC achieves SNDR 46.121 dB with ENOB 7.369-bit and consumes a power of 284 μW, resulting FoMW 17.28 fJ/conversion-step.

摘要        i
Abstract        ii
誌謝        iii
Contents        iv
List of Figures    viii
List of Tables    xiii
Chapter 1    Introduction    1
1    Performance Metrics of ADC    3
1.1    Nyquist Sampling Theorem    4
1.2    Resolution    5
1.3    Quantization Error    6
1.4    Offset and Gain Error    8
1.5    Differential Nonlinearity (DNL)    9
1.6    Integral Nonlinearity (INL)    10
1.7    Signal-to-Quantization-Noise Ratio (SQNR)    11
1.8    Signal-to-Noise Ratio (SNR)    11
1.9    Spurious-Free Dynamic Range (SFDR)    12
1.10    Signal-to-Noise and Distortion Ratio (SNDR)    12
1.11    Effective Number of Bits (ENOB)    12
1.12    Walden Figure-of-Merit (FoMW)    13
2    ADC Architecture    13
3    Target Specifications    14
4    Thesis Organization    16
Chapter 2    Successive Approximation Register (SAR) ADC Overview    17
1    Introduction of SAR ADC    17
2    Operation Procedure of Conventional SAR ADC    18
3    Sample and Hold (S/H) Circuit    19
3.1    On-Resistance of MOS Switch    20
3.2    Charge Injection    21
3.3    Clock Feedthrough    22
3.4    kT/C Noise    23
3.5    Sampling Jitter    24
4    Capacitive DAC (C-DAC)    25
4.1    Parasitic Capacitance    26
4.2    Mismatch of Capacitors    27
4.3    Settling Error    28
5    Dynamic Comparator    29
5.1    Input Referred Offset    31
5.2    Kickback Noise    32
6    Asynchronous SAR Logic    33
7    Summary    35
Chapter 3    Circuit Design Considerations    36
1    Differential SAR ADC    36
2    Sample and Hold (S/H) Circuit    37
3    Low-Voltage Time-Interleaved (LVTI) SAR ADC    38
4    Semi-Resting (SR) Switching    40
4.1    Switching Procedure    40
4.2    SR ADC in Time-Interleaved Architecture    43
5    Proposed Shared SR (SSR) Switching    44
5.1    Switching Procedure    45
5.2    MSB Decision Method    46
5.3    Non-Typical Sampling Clocks    47
6    Non-Ideal Effects of SSR Architecture    48
6.1    Sampling Clock Skew    48
6.2    Offset Error Mismatch    49
6.3    Gain Error Mismatch    51
7    Random Mode Assigning (RMA)    52
8    Summary    53
Chapter 4    Circuit Implementation of TI SAR ADC with SSR Switching    54
1    Proposed ADC Architecture    54
2    Design of Rotation Logic    55
2.1    Mode Assigning for Sub-ADCs    57
2.2    Utilization Order Regularity of The Sub-ADCs    59
2.3    Random Mode Assigning (RMA)    60
3    Sampling Clock Synchronization    62
4    Digital Offset Cancellation    64
5    Design of Polarity Detector (PD)    65
6    Design of Sample and Hold    67
7    Design of SAR Sub-ADCs    71
7.1    Cascade-Input (CI) Dynamic Comparator    73
7.2    Capacitive DAC (C-DAC)    75
7.3    INL-Splitting (INLS) DAC Switching    76
7.4    Asynchronous SAR Logic    80
8    Design of Data Readout Multiplexer    82
9    Summary    83
Chapter 5    Experimental Results    84
1    Pre-Layout Simulations    84
2    Post-Layout Simulations    85
3    Chip Micrograph    86
4    Measurement Environment Setup    87
5    Measurement Results    88
5.1    Single Sub-ADC Performance    88
5.2    Low Sampling Rate TI Performance    91
5.3    High Sampling Rate Performance    93
5.4    RMA Performance    97
6    Performance Summary and Comparison    99
7    Summary    101
Chapter 6    Conclusion and Future Work    102
1    Conclusion    102
2    Future Work    103
Bibliography    105
                                

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