科技進步飛快，人類對於細節的要求以及資訊的快速掌握也與日俱增，但是越高的細節也意味著龐大的資料量，這些巨量的資料將會嚴重影響獲取資料的速度，所以如何實現高速資料傳遞成為一個熱門的研究課題。
一個高速串列通訊電路(Serdes)分為接收端(RX)和發射端(TX)，其中接收端包含一個時脈資料回復電路(CDR)；發射端包含一個鎖相迴路電路(PLL)。本篇論文在研究一個操作在12GHz接收端的CDR電路，目的是使接收端能夠正確的取樣到發射端給的訊號。CDR電路相較PLL困難的點為：一般PLL電路的輸出訊號會經過除頻後再做比較，整體操作頻率(除了VCO)會與參考時鐘訊號相同；CDR整體電路基本上都是全速率在運作(也有半速率型的CDR電路，但是這邊不做討論)，所以對於子電路的帶寬(bandwidth)會有相當嚴格的要求。
本篇論文是採用類比式的CDR電路，雖然目前數位式的CDR電路相當火紅，但是經過操作頻率、模擬的精確程度以及佈局的寄生問題的權衡下我還是選擇採用類比式的作法。為了有效應付高速電路，本論文的相位偵測器是採用Bang-Bang架構的非線性相位檢測器，且使用壓流轉換器(V/I Converter)讓電流在短時間內能夠快速地切換，這個切換速率與CDR本身的追蹤抖動速率密切的相關。壓控震盪器我採用的是LC壓控震盪器，與環形壓控震盪器(Ring VCO)相比，LC壓控震盪器有更好的相位雜訊表現，但缺點為龐大的電感面積，所以在選擇架構時必須針對需求做改變。CDR電路最重要的評斷標準為抖動容忍(Jitter Tolerance)，我將會用抖動容忍角度去設計一個適合的迴路頻寬(loop bandwidth)，再做穩定度模擬。
本論文採用TSMC 65nm 1P9M製程，供應電壓為1.2V，目標為一個低自主雜訊的12GHz的全速率CDR電路。

With the rapid progress of science and technology, human's requirements for details and the rapid grasp of information are also increasing day by day. However, higher details also mean a huge amount of data, which will seriously affect the speed of data acquisition, so how to achieve high-speed data transmission has become a hot research topic.
A high-speed SerDes is divided into a RX and TX. RX includes a clock data recovery circuit (CDR). TX includes a phase-locked loop circuit (PLL). This paper is studying a CDR circuit operating at the 12GHz RX. The purpose is to enable RX to sample the signal given by the transmitter correctly. The difficulty of the CDR circuit compared with the PLL is : Generally, the output signal of the PLL circuit will be divided and then compared, and the overall operating frequency (except the VCO) will be the same as the reference clock . The overall CDR circuit is basically operating at full rate (there is also a half rate CDR circuit, but it will not be discussed here), so there will be quite strict requirements for the bandwidth of the subcircuit.
This paper uses an analog CDR circuit. Although digital CDR circuit is quite popular currently, I still decided to use the analog method because of the operating frequency, the accuracy of the simulation and the parasitic problems of the layout. In order to effectively cope with high-speed circuits, the phase detector in this paper is a Bang-Bang architecture which is a nonlinear phase detector. And the use of V/I Converter allows the current to switch quickly in a short period of time. This switching rate is closely related to the jitter tracking rate of the CDR.
I use LC voltage-controlled oscillator for the voltage-controlled oscillator. Compared with Ring VCO, LC VCO has better phase noise performance. The disadvantage is the large inductor area, so the architecture must be changed according to what you need. The most important criterion for evaluating CDR circuits is Jitter Tolerance. I will use the jitter tolerance to find a suitable loop bandwidth, then simulate the stability.
This paper is made of TSMC 65nm 1P9M with a supply voltage of 1.2V. The target is to design a 12GHz full-rate CDR circuit with low autonomous noise.

[1] Razavi, B. (2020). Design of CMOS phase-locked loops: from circuit level to architecture level: Cambridge University Press.
[2] Alexander, J. (1975). Clock recovery from random binary signals. Sep, 26, 541-542.
[3] Razavi, B. (2017). Design of Analog CMOS Integrated Circuits, edn., University of California, Los Angeles: McGraw-Hill Education.
[4] Kratyuk, V., Hanumolu, P. K., Moon, U.-K., & Mayaram, K. (2007). A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy. IEEE Transactions on Circuits and Systems II: Express Briefs, 54(3), 247-251.
[5] Tierno, J. A., Rylyakov, A. V., & Friedman, D. J. (2008). A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI. IEEE Journal of Solid-State Circuits, 43(1), 42-51.
[6] Razavi, B. (2012). Design of integrated circuits for optical communications: John Wiley & Sons.
[7] 高曜煌. (2005). 射頻鎖相迴路 IC 設計: 滄海.
[8] Amirkhany, A. (2020). Basics of clock and data recovery circuits: Exploring high-speed serial links. IEEE Solid-State Circuits Magazine, 12(1), 25-38.
[9] Andreani, P., Wang, X., Vandi, L., & Fard, A. (2005). A study of phase noise in Colpitts and LC-tank CMOS oscillators. IEEE Journal of Solid-State Circuits, 40(5), 1107-1118.
[10] Sengupta, K., & Hashemi, H. (2006). Maximum frequency of operation of CMOS static frequency dividers: Theory and design techniques. Paper presented at the 2006 13th IEEE International Conference on Electronics, Circuits and Systems.
[11] Sulivan, P., Xavier, B., & Ku, W. (1997). Low voltage performance of a microwave CMOS Gilbert cell mixer. IEEE Journal of Solid-State Circuits, 32(7), 1151-1155.
[12] Lee, J., Kundert, K. S., & Razavi, B. (2004). Analysis and modeling of bang-bang clock and data recovery circuits. IEEE Journal of Solid-State Circuits, 39(9), 1571-1580.
[13] Liang, J. (2017). On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits. University of Toronto (Canada).