在這篇論文中，我們提出了一個以線性規劃為基礎的漸進式平面規劃來最小化覆晶式設計的輸入輸出訊號歪斜。在線性規劃的模型中，我們加入了三種不同類型的限制條件。拓撲學的限制條件用來維持平面規劃的合法性。計算歪斜的限制條件用來計算輸入輸出訊號歪斜的量。當最小化歪斜的時候，使用約束線長的限制條件來約束線長的增加量。實驗結果顯示出使用漸進式平面規劃對於輸入輸出訊號歪斜可以有10%到31%的改善並且總線長的增加量可以被控制在可接受的範圍中甚至是獲得改善。

In this thesis, we propose a linear programming-based incremental floorplanning algorithm
to minimize the I/O signal skew for flip-chip design. In the linear programming, we add
three types of constraints. The topological constraints are used to keep the legality of the
floorplan. The skew evaluation constraints are used to evaluate the I/O signal skew. The
wirelength restriction constraints are used to restrict wirelength increase when minimizing
the skew. Experimental results show that I/O signal skew can be improved from 10% to
31%, and the increase of total wirelength can be controlled in an acceptable range or even
improved.

[1] C.-Y. Wang, W.-K. Mak, “Signal skew aware floorplanning and bumper signal assignment
technique for flip-chip,” in Proceedings of IEEE Asia-South Pacific Design Automation
Conference, 2009, pp. 341–346.
[2] C.-Y. Peng, W.-C. Chao, Y.-W. Chang, J.-H. Wang, “Simultaneous Block and I/O
Buffer Floorplanning for Flip-Chip Design,” in Proceedings of IEEE Asia-South Pacific
Design Automation Conference, 2006, pp. 213–218.
[3] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, S.-W. Wu, “B*-trees: A New Representation
for Non-slicing Floorplans,” in Proceedings of of ACM/IEEE Design Automation Conference,
2000, pp. 458–463.
[4] G. Pascariu, P. Cronin, and D. Crowley, “Next generation electronics packaging utilizing
flip chip technology,” in Proceedings of IEEE Electronics Manufacturing Technology
Symposium, 2003, pp. 423–426.
[5] M.-F. Lai, H.-M. Chen, “An Implementation of Performance-Driven Block and I/O
Placement for Chip-Package Codesign,” in Proceedings of IEEE International Symposium
on Quality Electronic Design, 2008, pp.604–607.
[6] H.-Y. Hsieh and T.-C. Wang, “Simple Yet Effective Algorithms for Block and I/O
Buffer Placement in Flip-Chip Designs,” in Proceedings of IEEE International Symposium
on Circuits and Systems, 2005, pp.1879-1882.
[7] X. Li, Y. Ma, X. Hong, S. Dong, “An Analytical Approach to Incremental Floorplanning,”
in Proceedings of IEEE International Conference on Communications, Circuits
and Systems, 2007, pp. 1145-1149.
[8] Z. Wang, Y. Ma, S. Dong, Y. Wang, X. Hong, “Incremental I/O Planning with White
Space Redistribution for Flip-chip Design,” in Proceedings of IEEE International Conference
on Communications, Circuits and Systems, 2010, pp.866–870.
[9] Z. He, Y. Ma, N. Xu, Y. Wang, X. Hong, “On Handling Fixed Blocks in Incremental
Fixed-outline Floorplanning,” in Proceedings of IEEE International Conference on
Communications, Circuits and Systems, 2010, pp.876–880.
[10] X. Li, Y. Ma, X. Hong, “A Novel Thermal Optimization Flow Using Incremental
Floorplanning for 3D ICs,” in Proceedings of IEEE Asia-South Pacific Design Automation
Conference, 2009, pp. 347–352.
[11] H. Ren, S. Dutt, “Constraint Satisfaction in Incremental Placement with Application
to Performance Optimization under Power Constraints,” in Proceedings of IEEE International
Conference on Computer Design, 2007, pp. 251–258.
[12] S. Dutt, H. Ren, “Discretized Network Flow Techniques for Timing andWire-Length
Driven Incremental Placement With White-Space Satisfaction,” in Proceedings of
IEEE Transactions on Very Large Scale Integration Systems, 2011, pp.1277-1290.
[13] X. Zhang, T. Takeuchi, M. Toyonaga, “AKEBONO: A Novel Quick Incremental
Placer,” in Proceedings of IEEE International Conference on IC Design and Technology,
2009, pp.51–53.
[14] L. Huang, Y. Cai, Q. Zhou, X. Hong, J. Hu, Y. Lu, “Clock Network Minimization
Methodology Based On Incremental Placement,” in Proceedings of IEEE Asia-South
Pacific Design Automation Conference, 2005, pp. 99–102.
[15] http://www.design-reuse.com/articles/7412/dynamic-floorplanning-a-practicalmethod-
using-relative-dependencies-for-incremental-floorplanning.html
[16] http://www.gurobi.com/
[17] http://cc.ee.nthu.edu.tw/ywchang/research.html
[18] http://www.duke.edu/ hpgavin/gnuplot.html