研究生: |
鄒輝麟 Hei-Lin Tsou |
---|---|
論文名稱: |
歐規與日規數位電視廣播系統之整合基頻接收機設計 Design of an Integrated Baseband Receiver for DVB-T、DVB-H and ISDB-T Standards |
指導教授: |
黃元豪
Yuan-Hao Huang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 82 |
中文關鍵詞: | 數位電視廣播系統 、整合基頻接收機 、模式偵測 、基頻通道 、歐規數位電視廣播系統 、日規數位電視廣播系統 |
外文關鍵詞: | DVB-T, DVB-H, ISDB-T, OFDM, Baseband Channel, Mode Detector |
相關次數: | 點閱:3 下載:0 |
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在本論文中,我們基於OFDM的這個主要技術去整合了歐規的地上數位廣播系統(DVB-T)以及手持移動式數位廣播系統(DVB-H)還有日規的數位廣播系統(ISDB-T)的系統架構,訂出整合的規格跟參數,並實作出一個整合基頻接收機。其中先用C++程式語言去模擬傳送端、基頻通道跟接收端的架構,傳送端部分,按照各個的數位電視廣播系統的規格去做訊號的時間或是頻率上打散跟排列以及插入不同領航碼,來降低錯誤率跟提高錯誤更正能力,最後經過反向快速傅立葉轉換後送入模擬基頻通道中,基頻等效通道模型包括多路徑衰減通道(Multipath Fading Channel)、都卜勒效應(Doppler Effect)、載波頻率漂移(Carrier Frequency Offset,CFO)、取樣時脈漂移(Sampling Clock Offset,SCO)以及加成性白色高斯雜訊(Additive White Gaussian Noise,AWGN)等通道非理想效應。最後在模擬接收機的模式偵測部分,因為在接收端需要判斷出為何種系統,快速傅立葉點數為何以及Guard-Interval Ratio的長度,才能作下面一系列各種通道非理想效應的估測跟補償,所以根據系統不同的取樣頻率跟延遲相關(Delay Correlation)的方程式去做模式的偵測,知道模式後就可以結合符元時序偵測(Symbol Timing Detection)、載波頻率漂移(CFO)與取樣時脈漂移(SCO)估測、追蹤與補償、2K-4K-8K 快速傅立葉處理器(2K-4K-8K FFT Processor)、相位調整(Phase Modification)及通道估測(Channel Estimation)與補償等演算法實現整合的基頻接收機系統。在硬體電路方面,設計電路的架構與圖形,並且是使用輸出訊噪比(Output SNR)取代位元錯誤率(Bit Error Rate,BER)來作為取最佳位元數的指標,最後用硬體描述語言跟最佳位元數去做硬體電路的模擬與實現。
In this thesis, we propose an integrated system architecture, which is based on the concept of OFDM, for DVB-T、DVB-H and ISDB-T systems. The baseband equivalent channel model includes effects of multipath fading channel, Doppler Effect, Carrier Frequency Offset, Sampling Clock Offset and Additive White Gaussian Noise. In the receiver part, because the receiver need to detect the correct system mode、FFT size and Guard-Interval Ratio length in the beginning, so we according to the different sampling rate between systems and delay correlation function to realize the mode detection, and combines algorithms of symbol timing detection, CFO and SCO estimation, compensation, and tracking, 2K-4K-8K FFT processor, phase modification and channel estimation and compensation. In hardware circuit design, this thesis uses output SNR instead of Bit Error Rate as the metric of optimum word length. Finally, we realize the hardware circuit simulation and implementation by Verilog HDL.
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