近年來消費性電子產品，在市場需求輕薄短小、速度快、多功能以及美觀的綜合需求下，線路密度越來越高，導線體積卻越來越小，傳統鋁或銅導線的接合技術因體積龐大加上可使用接點少至現在已不敷使用，因而發展了覆晶封裝技術。此一技術提供單位面積上更多的接點，同時減少了所需的體積，但因為體積縮小，導體中電流密度增加，在更高的操作溫度下，電遷移所產生的破壞便會發生而造成了產品可靠度的問題。現今為了追求更高的產品表現以及更小的體積進而發展了三維立體封裝的技術，其使用的微型焊錫球與直通矽晶穿孔技術，可望達成更高效能以及更進一步減少體積的目標。然而，當尺寸再度縮小同時又必須維持高功率的表現時，可靠度問題勢必成為這一新興技術所面臨最重要挑戰。
　　此篇論文中將探討三維立體封裝中之電遷移破壞機制。試片中使用的是Sn2.5Ag微型焊錫，凸塊底層金屬為Cu/Ni。研究發現相較於傳統覆晶封裝技術中之焊錫球，三維立體封裝技術中之微型焊錫球有更高的電遷移抗性並可以承受更高的電流密度，這是歸功於相對來說更厚的凸塊底層金屬以及較小之焊錫球高度。當電流密度低於 2x104A/cm2 時，試片中看不出有電遷移所導致的破壞。考慮背向應力所帶來的影響，我們計算出於三維立體封裝中微型焊錫臨界電流密度為 7.5x104A/cm2。不過，當施加之電流密度超過此值時，於150度烤箱內的試片並沒有發現焊錫內部有空孔產生；反之，空孔出現在陰極端的鋁導線內。進一步研究鋁導線產生電遷移的破壞時間，我們可以算出其電流密度次方係數為 1.78，而其活化能為 1.22 電子伏特。

Nowadays, due to the trend in having multiple functions and greater performance of consumer electronic products, traditional Al or Cu wire bonding technology is insufficient to serve this high density packaging. Flip chip technology was then developed to meet the requirement to have denser I/O array, smaller feature size of joints, and higher power. At this time, serious reliability problems were discovered as the result of electromigration due to higher current density applied in the solder bumps, and higher operating temperature. For further demands on multifunction, higher performance and rather smaller size, three-dimensional integrated circuit (3D IC) packaging technology is regarded as a promising future to meet those needs. As a result, micro bumps and through silicon via (TSV) are employed; however, with greater increased current density, the performance is highly affected by the reliability problems, and the failure mechanism of electromigration in this newly developed technology requires further studies.

In this thesis, electromigration-induced failure on Sn2.5Ag lead-free micro bumps with Cu/Ni under bump metallization (UBM) and chip-on-chip (COC) configuration in three-dimensional integrated circuit samples were studied. Compared to flip chip solder joints, micro bumps in 3D IC samples exhibit better electromigration resistance and are capable to withstand a higher current density, which are attributed to the presence of thicker UBM and short bump height. No exhibited electromigration-induced failure was observed when current density was below 2x104A/cm2. After considering the effect of back stress, threshold current density to trigger electromigration in chip-on-chip samples was estimated to be 7.5x104A/cm2. When current density was higher than 7.5x104A/cm2 at an ambient temperature of 150oC, no void propagation through the whole bump opening was found; instead, electromigration-induced voids were observed at the cathode side of Al trace. The time-to-failure (TTF) of Al trace on three-dimensional integrated circuits was also studied, and the current density exponent (n) and the activation energy (Ea) were calculated as 1.78 and 1.22 eV, respectively.

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