在消費性電子產品的快速發展下，為了滿足高效能、體積小和多功能的需求，在封裝技術上也作了提升，在覆晶封裝技術中，其提供了相同面積下更多的I/O數，同時減少了所需的體積，然而接點體積的縮小造成了更大的電流密度和更高的工作溫度環境，因此近年來電遷移破壞成為產品可靠度的重要問題，此外新發展的三維立體封裝技術，其利用微型銲錫球與直通矽晶穿孔技術作為堆疊和連結不同的晶片，達到了微型化和更高效能的要求，但伴隨而來的可靠度問題勢必將成為其發展的關鍵。
針對銲錫體積的縮減和更厚的凸塊底層金屬使用，本論文主要討論銲錫高度對電遷移效應下銅底層金屬消耗的影響，在實驗中，我們利用不同長度的線性型銅/錫/銅結構作電遷移觀察，此結構可避免掉其他複雜的效應，例如電流擁擠效應或溫度梯度的影響等，進而對電遷移效應有更直接的討論，藉由微影製程和電鍍技術，試片中包含 300, 150, 100, 75, 50和25 μm的各種銲錫長度，當通入電流密度3x103 和 8x103 A/cm2 、溫度設定在75℃的電遷移實驗下，實驗結果觀察到兩種破壞機制，分別為孔洞的生成及陰極端介金屬化合物的溶解，並發現此兩種破壞機制都與銲錫的高度有關。隨著銲錫高度的增加，孔洞的生成更加嚴重。此外隨著銲錫高度的增加，電遷移造成陰極端介金屬化合物有嚴重的消耗，另外由實驗結果也可以發現，當銲錫高度縮減達到一臨界長度時，銲錫中不會觀察到電遷移所造成的介金屬化合物溶解。在此研究中我們分別提出誘發孔洞破壞及介金屬化合物溶解的臨界長度，並深入探討提出解釋此兩種現象的機制，由以上研究可進一步了解電遷移效應下不同銲錫高度對電遷移破壞行為的影響。

Under the rapid development of consumer electronics products, the packaging technique had also improved in order to meet the demand for high performance, small size and multi-function. In the flip chip packaging technology, it provides more I/O counts with same area, while reducing the size. However, with smaller solder bump, an increase in current density is enough to cause the electromigration in flip chip solder joint. Thus, electromigration has become a serious reliability problem in recent years. In addition, the three-dimensional integrated circuit (3D IC) packaging technology has been developed for the further demands on higher performance and miniaturization of electronics products, which using the microbumps and through silicon vias (TSV) to stack and connect with different silicon chip. With much smaller solder bump and greater increased current density, more severe reliability issue is expected to be the key to this new developing technology.
In this thesis, the effect of solder length on void formation and IMCs dissolution under current stressing was discussed, especially when 3D IC technology used smaller solder bumps decreased and thicker Cu metallization. The electromigration tests were performed on the line-type Cu/Sn/Cu solder strips in order to direct investigation of electromigration effect, which excluding others complicated factors, i.e. current crowding effect and temperature gradient. By using photolithography and sputtering, the solder strips of various lengths, including 300, 150, 100, 75, 50 and 25 μm, can be fabricated. Two main failure behaviors were found to be affected by solder length under current stressing, including the void formation induced by the diffusion of Sn and the IMCs dissolution induced by the diffusion of Cu under current stressing by 3×103 and 8×103A/cm2 at 75°C. Both failure behaviors become more serious when the solder length increases. The corresponding mechanism and kinetic analysis for both length-dependent void formation and dissolution of IMCs was discussed. Moreover, no electromigration induced void formation and dissolution of IMCs was observed at certain solder length. The critical length to trigger dissolution of IMCs under current stressing was also obtained. Through the results in this thesis, the effect of solder length on electromigration behavior under current stressing was further clarified.

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