隨著資料儲存與處理量增加，光通訊在近期成為一個熱門的研究題目。在此篇論文中，我們著重在設計高速光通訊的傳輸端電路。前四章在介紹使用不同方法與製程設計的調變器驅動電路，第五章則是使用90nm CMOS來設計一個雷射二極體驅動電路，最後一章將作出結論。
第二章裡，運用電感增加頻寬的40 Gb/s 分散是放大器被實作於標準90 nm CMOS製程中，在6 V的供應電壓下此電路消耗408 mW，在25 Gb/s的運作速度下可以有2.5 V的電壓擺伏，在40 Gb/s的運作速度下可以有1.5 V的電壓擺伏。晶片面積為1 × 0.5 mm2。
第三章裡，40 Gb/s的調變器驅動電路被實作於標準40 nm CMOS 製程中，此電路的主要目的是要跟University of Southampton Optoelectronics Research Center所提供的調變器做結合。在負載50歐姆的狀況下，此調變器驅動電路在12.5 Gb/s與25 Gb/s的速度中可達到1.76 Vpp 與1.41 Vpp，而在供應電壓維2/4 V的情形下此電路消耗功率為308 mW，而電路大小為0.62 × 0.53 mm2。
第四章裡，40 Gb/s的調變器驅動電路被實作於 0.13 μm SiGe，此製成是由Innovations for High Performance Microelectronics 或 IHP所提供，此電路的3-dB頻寬可達到51.8 GHz而且在5 V的供應電壓下消耗功率為389 mW，此電路擁有2.35 V的電壓擺伏，晶片面積為650 × 450 mm2。
第五章裡，25 Gb/s的雷射二極體驅動電路透過圖騰柱與不對稱電感被實作於90 nm CMOS製程。圖騰柱可以將差動電路轉為單端，而不對稱的電感則提供足夠的增益給上下兩路訊號路徑。這個雷射二極體驅動電路在2V的供應電壓下消耗125.4 mW 並提供35 mA的調變電流。
關鍵詞:分散式放大器、調變器驅動電路、雷射二極體驅動電路、光連結系統、三維電感

With the rapid growth of computing and data storage, optical communication has become a popular research topic recently. In this thesis, we focus on designing high speed transmitters of optical communications. The first four chapters show the design and implementation of modulator drivers in different topologies and technologies. In chapter five, the 90nm CMOS technology is used to design a laser diode driver. Finally, a conclusion is given in chapter six.
In chapter 2, a 40 Gb/s distributed amplifier (DA) with an inductor peaking technique in 90 nm CMOS has been implemented. The power consumption of the DA was about 408 mW under a supply voltage of 6 V. The DA reaches a voltage swing over 2.5 V with an operation speed of 25 Gb/s and 1.5 V swing at 40 Gb/s. The chip area is 10.5 mm2. The measurement results show this design is capable of 25 Gb/s operation.
In chapter 3, a compact 40 Gb/s modulator driver is proposed and implemented in 40 nm CMOS for the purpose of integration with the silicon-based high speed modulator, provided by University of Southampton Optoelectronics Research Center. Under the termination of 50 , the modulator driver can reach a 1.76 V peak-to-peak voltage swing (Vpp) and 1.41 V_PP at the speed of 12.5 Gb/s and 22 Gb/s respectively under electrical measurements. Also, the extinction radios are 4.9 dB and 3.27 dB at 10 Gb/s and 20 Gb/s for optical measurements. The power consumption is 308 mW and the area is 0.62  0.53 mm2.
In chapter 4, a 40 Gb/s inductorless modulator driver is proposed and implemented in 0.13-μm SiGe BiCMOS technology, provided by the Innovations for High Performance Microelectronics (IHP). The simulated results show a 3-dB bandwidth up to 51.8 GHz while consuming 389 mW under a supply voltage of 5 V. The voltage swing is 2.35 V and the chip area is 650  450 mm2. The simulated eye diagram is well opened at the speed of 40 Gb/s.
In chapter 5, a laser diode driver incorporating the proposed totem pole output stage and asymmetric inductors can achieve a voltage gain of 2.5 dB and a bandwidth of 16.5 GHz with a power consumption of 125.4 mW. A driver using the totem pole configuration can easily transfer the differential signal to single ended. With the proposed asymmetric inductors, both signal paths will have a similar gain leading to a good characteristic of eye diagram. This driver can operate at 25 Gb/s while delivering 70 mA to the load of a 10-Ω laser diode. The circuit is fabricated in 90 nm CMOS technology, operating with a 2-V supply.
Keywords: Distributed amplifier, Modulator driver, Laser diode driver, Optical interconnect system, and 3D inductor.

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