中 文 摘 要
金屬(Al)/氧化鉿(HfO2)/半導體(p-Si)結構的電容器、N通道場效電晶體與P通道場效電晶體在本實驗中成功以RF sp被製造。以氧化鉿為絕緣層的電容器在|VG－VFB|＝1V的偏壓下漏電流為0.02 A/cm2，其介電常數k值從電容器C-V曲線得到為12。對電容器作變溫電性量測，以討論漏電流機制，結果顯示當溫度達498K左右且電場為1.2~1.8MV/cm時，在Al/HfO2介面的漏地流傳導機制為蕭基發射所主導。對電晶體而言，改變300K到420 K的溫度變化來探討N通道電晶體特性的溫度相依關係。透過使用split-C-V方法來萃取通道中載子遷移率，其中對N通道電晶體的電子遷移率是172 cm2/V-s，而P通道電晶體的電洞遷移率是16 cm2/V-s。對於N通道的電子遷移率衰減機制在本實驗中是被探討的，被聲子散射限制住的電子遷移率在固定有效電場為0.5 MV/cm且溫度變化從300到420 K下是正比於T-2.24，而被表面粗糙散射限制住的電子遷移率在室溫下且有效電場為0.5-1.2 MV/cm時是正比於Eeff-0.56。
從電晶體的漂移-擴散理論得到的載子遷移率在奈米尺度下並不是一個明確的數量值，其中電晶體的單通量散射理論是在文獻中被引入來取代在小尺寸的電子遷移率，以HfO2為閘極氧化層電晶體的通道散射是被探討的，而其背向散射因子(backscattering coefficient)成功的在本實驗中量測出來，數值為0.51-0.11相對應的通道長度為40μm到8μm，對於相關的背向散射因子的詳細分析將在文章中介紹。
至於材料物性方面，作了二次質譜儀縱深分佈 (Secondary Ion Mass Spectrometry : SIMS)、原子力顯微鏡 (Atomic force microscope : AFM)、X光繞射 (X-Ray Diffraction : XRD)等物性分析與原子力顯微鏡 (Atomic force microscope : AFM) 分析。

Abstract
Metal-insulator-semiconductor (MIS) capacitors, n-channel and p-channel metal-oxide-semiconductor (MOS) transistors with HfO2 gate dielectric were fabricated. The HfO2 films were deposited by RF sputtering. The leakage current of MIS capacitors is 0.02 A/cm2 at |VG-VFB| = 1V. Schottky emission is found to be the dominating mechanism at 498 K in the electric field from 1.2 MV/cm to 1.8 MV/cm. The temperature dependence of NMOS transistor characteristics was studied in the temperature range from 300 K to 420 K. The carrier mobility is measured by the split C-V method. The maximum mobility of NMOS transistor is 172 cm2/ V-s while the maximum mobility of PMOS transistor is 16 cm2/ V-s. The mobility degradation mechanism of NMOS transistor was studied. The electron mobility limited by phonon scattering is proportional to T-2.24 at the effective normal field Eeff of 0.5 MV/cm between 300 K and 420 K. The electron mobility limited by surface roughness is proportional to Eeff-0.56 in the fields of 0.5＜Eeff＜1.2 MV/cm at 300 K.
The mobility is an important parameter in traditional drift-diffusion theories of MOS transistor, but it is not a well-defined quantity in nanoscale MOS transistors. In this work, the experimental results were compared with the one-flux scattering theory. The backscattering of electrons of NMOS transistor with HfO2 gate dielectric was studied. The backscattering coefficient rc is obtained by measuring the temperature dependence of the drain current. The value of rc is in the range 0.11-0.51 with the gate length varying from 8 μm to 40 μm.

References
[1] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447-449, 1997.
[2] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823-4829, 1998.
[3] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage current comparison between ultra-thin Ta2O5 films and conventional gate dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341-342, 1998.
[4] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor characterization with Ta2O5 gate dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp.441-443, 1998.
[5] B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance -voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087-4093, 1999.
[6] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and characterization of metal-oxide-semiconductor field-effect transistors and gated diodes using Ta2O5 gate oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537-539, 2000.
[7] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon barrier height measured from MOSFETs fabrication with Ta2O5 gated dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221-223, 2001.
[8] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, M. C. Stock, Z. Yu, and M. Zeitzoff, “The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1537-1544, 1999.
[9] J. Y. Lee and B. C. Lai, Ferroelectric and dielectric thin films, edited by H. S. Nalwa, New York: Academic press, 2001.
[10] A. I. Kingon, J. P. Maria, and S. K. Streiffer, “Alternative dielectrics to silicon dioxide for memory and logic devices,” Nature, vol. 406, no. 6799, pp.1032-1039, 2000.
[11] M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J. Tobin, “Thermodynamic stability of high-k dielectric metal oxide ZrO2 and HfO2 in contact with Si and SiO2,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1897-1899, 2002.
[12] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor characterization with Ta2O5 gate dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441-443, 1998.
[13] W. J. Zhu, T. P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in metal/ hafnium oxide/ silicon structure,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 97-99, 2002.
[14] B. K. Park, J. Park, M. Cho, C. S. Hwang, K. Oh, Y. Han, and D. Y. Yang, “Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing,” Appl. Phys. Lett., vol. 80, no. 13, pp. 2368-2371, 2002.
[15] D. A. Neumayer, and E. Cariter, “Materials characterization of ZrO2-SiO2 and HfO2-SiO2 binary oxides deposited by chemical solution deposition,” J. Appl. Phys., vol. 90, no. 4, pp. 1801-1808, 2001.
[16] H. Lee, S. Jeon, and H. Hwang, “Electrical characteristics of Dy-doped HfO2 gate dielectric,” Appl. Phys. Lett., vol. 79, no. 16, pp. 2615-2617, 2001.
[17] A. Callegari, E. Cariter, H. F. Okorn-Schmidt, and T. Zabel, “Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films,” J. Appl. Phys., vol. 90, no. 12, pp. 6466-6475, 2001.
[18] W. Zhu, J.-P. Han, and T. P. Ma, “Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics,” IEEE Trans. on Electron Device, vol. 51, no. 1, pp. 98-105, 2004.
[19] J. S. Kang, D. K. Schroder, and A. R. Alvarez, “Effective and field-effect mobility in Si MOSFETs,” Solid-State Electronics, vol. 32, no. 8, pp. 679-685, 1989.
[20] M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., vol. 18, no. 7, pp. 361-363, 1997.
[21] H.-N. Lin, H.-W. Chen, C.-H. Ko, C.-H. Ge, H.-C. Lin, T.-Y. Huang, and W.-C. Lee, “Channel backscattering characteristics of uniaxially strained nanoscale CMOSFETs,” IEEE Electron Device Lett., vol. 26, no. 9, pp. 676-678, 2005.
[22] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 181-183, 2000.
[23] S. Lee et al, “High quality ultra thin CVD HfO2 gate stack with poly-Si gate electrode,” Symp. VLSI Tech. Dig., pp. 31-34, 2000.
[24] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mater. Res., vol. 11, no. 11, pp. 2757-2776, 1996.
[25] Z. J. Luo and T. P. Ma, “Ultra-thin ZrO2 (or silicate) with high thermal stability for CMOS gate application,” Symp. VLSI Tech. Dig., PP.135-136, 2001.
[26] Y. Kim, G. Gebara, M. Frelier, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B. Foran, F. Shappur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givans, M. Mazanez, and C. Werkhoven, “Conventional n-channel MOSFET device using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” IEDM Tech. Dig.,2001, pp. 455-458.
[27] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advance gate dielectrics,” J. Appl. Phys., vol. 87, no. 1, pp. 484-492, 2000.
[28] M. Balog, M. Schieber, M. Michman, and S. Patai, “Chemical vapor deposition and characterization of HfO2 films from organo-hafnium compounds,” Thin Solid Films., vol. 41, no. 1, pp. 247-254, 1997.
[29] S. M. Sze, Physics of semiconductor device, 2nd ed., Wiley, New York, 1981.
[30] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO2 and Zr silicate gate dielectrics,” IEDM Tech. Dig., 2000,pp. 27-30.
[31] J. R. Yeargan, H. L. Taylor, “The Poole-Frenkel effect with compensation present,” J. Appl. Phys. vol. 39, no. 12, pp. 5600-5604, 1968.
[32] S. G. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxided silicon surfaces,” IEEE Trans. Electron Devices, vol. 27, pp. 1497-1508, 1980.
[33] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, “Improved split C-V method for effective mobiltiy extraction in sub-0.1-μm Si MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 8, pp. 583-585, 2004.
[34] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration”, IEEE Trans. Electron Devices, 41, pp. 2357-2362, 1994.
[35] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors,” Solid State Electronics, vol. 25, no. 9, pp. 833-841, 1982.
[36] J. Kang, D. Schroder, and A. Alvarez, “Effective and field-effect mobiltiy in Si MOSFETs,” Solid State Electronics, vol. 25, no. 8, pp. 679-682, 1989.
[37] W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, ”Estimating oxide thickness of tunnel oxide down to 1.4 nm using conventional capacitance-voltage measurement on MOSD capacitors”, IEEE Electron Device Lett., vol. 20, pp. 179-181, 1999.
[38] V. V. Afanas’ev and A. Stesmans, ”Hydrogen-induced valence alternation state at SiO2 interfaces,” Phys. Rev. Lett., vol. 80, pp. 5176-5179, 1998.
[39] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, 1st ed. Cambridge University press, 1998.
[40] G. Baccarani, and M. R. Wordeman, “Transconductance degradation in thin-oxide MOSFET’s,” IEEE Trans. Electron Devices, vol. 30, pp. 1295-1304, 1983.
[41] W. J. Zhu and T. P. Ma, “Temperature dependence of channel mobility in HfO2-gated NMOSFETs,” vol. 25, no. 2, pp. 89-91, 2004.
[42] M. T. Wang, B. Y. Y. Cheng, and J. Y. Lee, “Temperature dependence degradation mechanisms of channel mobility in ZrO2-gated n-chanel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, pp. 242905-1-242905-3, 2006.
[43] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, “Effective electron mobility in Si inversion layers in metal–oxide–semiconductor systems with a high- insulator: The role of remote phonon scattering”, J. Appl. Phys. 90, pp. 4587-4608, 2001.
[44] S. E. Laux and M. V. Fischetti, “Monte Carlo simulation of submicrometer Si n-MOSFET’s at 77 and 300 K,” IEEE Electron Device Lett., vol. 9, pp. 467-469, 1988.
[45] M. R. Pinto, E. Sangiorgi, and J. Bude, “Silicon MOS transconductance scaling into the velocity overshoot regime,” IEEE Electron Device Lett., vol. 14, pp. 37-5378, 1993.
[46] S. Y. Chou, D. A. Antoniadis, and H. I. Smith, “Observation of electron velocity overshoot in sub-100-nm-channel MOSFET’s in Si,” IEEE Electron Device Lett., vol. 6, pp. 665-673, 1985.
[47] G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, S. Rishton, and E. Ganin, “High transconductance and velocity overshoot in NMOS at the 0.1-um gate-length level,” IEEE Electron Device Lett., vol. 8, pp. 464-466, 1988.
[48] M. J. Chen, H. T. Huang, K. C. Huang, P. N. Chen, C. S. Chang, and C. H. Diaz, “Temperature dependent channel backscattering coefficients in Nanoscale MOSFETs,” IEDM Tech. Dig., 2002, pp. 39-43.
[49] Y.Taur, C. Wann, and D. Frank, “25 nm CMOS design considerations,” IEDM Tech. Dig., pp.789-792, 1998.
[50] A. Lochteldef and D. A. Antoniadis, “On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?” IEEE Electron Device Lett., pp. 95-97, 2001.
[51] F. Assad, Z. Ren, S. Datta, and M. S. Lundstrom, “Performance limits of silicon MOSFET’s,” IEDM Tech. Dig., 1999, pp. 547-551.
[52] E. Fuch, P. Dollfus, G. L. Carval, S. Barraud, D. Villanueva, F. Salvetti, H. Haouen, and T. Skotnicki, “A new backscattering model giving a description of the quasi-ballistic transporting nano-MOSFET,” IEEE Trans. Electron Device, vol. 52, no. 10, pp. 2280-2289, 2005.
[53] H. N. Lin, H. W. Chen, C. H. Ko, C. H. Ge, H. C. Lin, T. Y. Huang, and W. C. Lee, “Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain,” IEDM Tech. Dig., 2005, pp. 141-145.