在本篇論文第一個章節中，首先針對星狀型磁性隨機存取記憶體 (asteroid MRAM) 的元件結構與基本操作原理做一個簡介，接下來展示磁性穿隧元件 (MTJ) 多層膜之磁性特性。針對目前磁性隨機存取記憶體遭遇到的種種問題點探討，以及尋求解決之道，成為本論文研究的動機。
在本篇論文第二個章節中，提出一種含側邊金屬柱寫入線 (PWWL) 的記憶細胞元，擁有與互補式金氧半 (CMOS) 相容的製程步驟。除了一般之下邊寫入字元線 (WWL) 所感應產生的寫入磁場之外，電流流經一對的側邊金屬柱更提供了額外加強的感應磁場，作用在磁性細胞元之上。此結構比起傳統的結構，能夠大幅提昇感應磁場，因此將寫入電流下降了大約一半之多。當磁性記憶體持續微縮下去的時候，此增強磁場的效應會更加的顯著。接著，提出了一種採用一個電晶體搭配兩個尺寸非對稱的磁性穿隧元件 (1T2UMTJ) 之記憶元架構，藉由一種稱為延伸引洞 (ExtVia) 的製程步驟，理想上能夠將此記憶細胞元的位元尺寸下降到六個單位尺寸 (6 F2)。此結構亦能達成小於 50 奈秒的快速讀出流程，以及一次雙位元讀出的高資料傳輸速率。此外，進行多種參考值產生器的設計與比較，並提出兩種先天上處於中點訊號狀態的參考細胞元，可以應用在星狀型磁性記憶體，以及拴扣型磁性記憶體 (toggle MRAM)。此參考值細胞元，不僅可以做為強韌以及可靠的參考細胞元，並有機會做為資料儲存的記憶細胞元。
在第三個章節中，提出了兩種拴扣型磁性記憶體的操作方法，藉由預先產生的負向脈衝波形 (SNP)，以及雙向脈衝波形 (DNP) 的操作模式探討與研究，能夠將翻轉磁偶極矩的良率大幅提高，並使得在低寫入電流的操作變為可能。在微磁學模擬的分析中，拴扣型磁性記憶體的翻轉錯誤機制被發現與證實。藉由模擬與實驗的數據顯示，拴扣型磁性記憶體能夠操作在由下固定層產生較強的偏壓磁場，並讓磁性記憶體的寫入電流因而降低。藉由強韌的拴扣型操作，以及操作可靠度的提昇，達成較寬廣的操作區間，以及降低的寫入電流，使得磁性記憶體的微縮化得以持續。
在論文的第三章節中，提出了一種從一個電晶體搭配兩個尺寸非對稱的磁性穿隧元件 (1T2UMTJ) 修改的記憶架構，可以應用於拴扣型磁性記憶體的操作模式。此記憶架構，擁有小位元尺寸以及雙倍字元長度的優點，此外，藉由週邊輸入輸出電路的設計，有機會將此記憶架構應用在讀寫雙倍速率的操作模式。因此，擁有降低的位元尺寸，以及提昇的操作表現，使得磁性記憶體更能與目前的傳統半導體記憶體相互競爭。
在最後的章節當中，首先提出了兩種可應用於磁性記憶體的新穎記憶細胞元，並藉由微磁學模擬以驗證操作的動作與功效。由於這類的記憶細胞元，不僅可以儲存資料狀態，更可以供為感應放大器成為參考值訊號之用，因此記憶體內操作的負載得以較為平衡地作用在記憶元與細胞元之上，故提昇了記憶體的可靠度。藉由微磁學模擬以及實驗的數據顯示，一種稱為正交擾動 (orthogonal wiggle) 的記憶細胞元達成了接近全訊號的感應區間。透過一個包含模型化磁性穿隧元件的電路模擬，此正交擾動的記憶細胞元，達成高讀寫操作的功能展示。此外，藉由提出兩種新穎的記憶陣列架構，如鄰近參考架構 (adjacent-reference architecture)，以及自我參考架構 (self-reference architecture)，讀取功能性，以及記憶體晶片的可靠性得以大幅地提昇。
藉由本論文中各種創新的設計，由於如位元尺寸得以縮小、寫入電流得以降低、操作表現得以改善，更特別的，操作的正確率得以提昇、晶片功能性以及可靠性得以穩定，使得磁性記憶體達成接近量產的時程變得更加地有希望。

In the first chapter of this thesis, a brief introduction on asteroid type magnetic random access memory (MRAM) is presented followed by the exhibition of the magnetic characteristics of magnetic tunneling junction (MTJ) device. Several issues for MRAM technology are highlighted.
In the second chapter of this thesis, a novel MRAM cell with pillar write word line (PWWL) is proposed and integrates effortlessly with the complementary metal oxide semiconductor (CMOS) process. Asides from the magnetic field induced by the bottom write word line (WWL), an additional magnetic field is superimposed into the memory cell from the current flowing through the pair of PWWLs. This structure can significantly enhance the magnetic field and can thus reduce the writing current by approximately a factor of 2 as compared to the conventional structure. The field enhancement will be even more pronounced as the MRAM cell is further downsized. Following that, a novel cell structure based on one transistor and two uneven magnetic tunnel junctions (1T2UMTJ) is proposed to shrink the bit size with a potential decrease in size down to 6 F2 by using a so-called extended via (ExtVia) process. Consequently, a high reading speed and throughput of less than 50 ns accessing time for two sharing bits is realized. In addition, numerous reference generators are discussed and compared. Two kinds of inherent mid-value cells for asteroid MRAM and toggle MRAM are proposed, which can not only be used for the robust and reliable reference cell but also as a potential data-storage memory cell.
In the third chapter of this thesis, novel writing schemes with preceding single negative pulse (SNP) waveform and double negative pulse (DNP) waveform for toggle MRAM are proposed and studied to enhance the switching yield and enable a low current switching. The failure mechanism of toggle switching is studied by micromagnetic analysis. Both simulation results and measured data show that the toggle MRAM can be operated in low writing current at strong bias field. As a result of broadened operation window and reduced switching current, the scalability of MRAM is feasible with the robust toggle operation and improved reliability.
In the fourth chapter of this thesis, a modified 1T2UMTJ cell structure for toggle MRAM is proposed and discussed. The 1T2UMTJ toggle MRAM has the advantage on bit size and has a double word length. Besides, the 1T2UMTJ toggle MRAM has the potential to operate at a high read/write bandwidth using the proposed input/output circuitry. Consequently, with the reduced bit size and the improved operation performance, the MRAM becomes even more attractive compared with the conventional semiconductor memories.
In the fifth chapter of this thesis, two kinds of inherent mid-value cells for MRAM are proposed and studied by the micromagnetic simulation. Since the operation loading on such cells can be balanced, the memory and reference dual-role cell can enhance the chip’s reliability. The micromagnetic analysis and the experimental data shows that a near full magneto-resistance ratio (MR%) sensing margin is achieved by a so-called “orthogonal wiggle” MRAM cell. In addition, a fast read/write operation of MRAM is demonstrated by a MTJ-modeled SPICE simulation for the proposed orthogonal wiggle cell. Moreover, the read functionality and the chip reliability can be enhanced by the proposed adjacent-reference architecture and, particularly, the self-reference architecture.
With all the innovative designs, the mass production of MRAM becomes more feasible because of the shrunk bit size, the reduced switching current, the improved performance and, particularly, the enhanced switching accuracy and the stabilized chip functionality and reliability.

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[3.1] T. Tsuji, H. Tanizaki, M. Ishikawa, J. Otani, Y. Yamaguchi, S. Ueno, T. Oishi, and H. Hidaka, “A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture,” IEEE Symposium on VLSI Circuits, 450 (2004).
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[5.1] N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, and S. Tahara, “MRAM cell technology for over 500 MHz SoC”, in IEEE Symp. VLSI Circuits, Jun. 15-17 2006, pp. 136-137.
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A. Refereed Journal paper
1. S. Chao and Chien-Chung Hung, “Large photoinduced ferroelectric coercive field increase and photodefined domain pattern in lithium-tantalate crystal,” Appl. Phys. Lett., vol. 69 (25), pp. 3803-3805, Dec. 1996. [SCI, 4.31]
2. Chien-Chung Hung, M.J. Kao, W.C. Lin, S. Chao, D. Tang, and M.-J. Tsai, “Low writing current magnetoresistive random access memory (MRAM) with side metal pillar write word line (PWWL),” J. Magn. Magn. Mater., vol. 282c, pp. 373-379, Nov. 2004. [SCI, 1.03]
3. Chien-Chung Hung, Y.J. Lee, M.J. Kao, Y.H. Wang, R.F. Huang, W.C. Chen, Y.S. Chen, K.H. Shen, M.-J. Tsai, W.C. Lin, D. D.-L. Tang, and S. Chao, “Wide operation margin of toggle mode switching for magnetic random access memory with preceding negative pulse writing scheme,” Appl. Phys. Lett., vol. 88 (11), pp. 112501.1-112501.3, Mar. 2006. [SCI, 4.31]
4. Chien-Chung Hung, M.J. Kao, Y.S. Chen, Y.H. Wang, Y.J. Lee, W.C. Chen, W.C. Lin, K.H. Shen, K.L. Chen, S. Chao, D. D.-L. Tang, and M.-J. Tsai, “A 6-F2 bit cell design based on one transistor and two uneven magnetic tunneling junctions structure and low power design for MRAM,” IEEE Trans. Electron Devices, vol. 53 (7), pp. 1530-1538, July 2006. [SCI, 2.04]
5. Chien-Chung Hung, Y.J. Lee, Y.H. Wang, D.Y. Wang, W.C. Chen, Y.S. Chen, M.-J. Tsai, M.J. Kao, and S. Chao, “Inherent mid-value cell for magnetic random access memory with full signal sensing margin”, Appl. Phys. Lett., submitted, May. 2006. [SCI, 4.31]
6. Y.H. Wang, W.C. Chen, Y.S. Chen, K.H. Shen, Y.J. Lee, Chien-Chung Hung, C.M. Chen, H.H. Hsu, W.S. Chen, D.C. Liu, M.J. Kao, L.C. Wang, C.H. Lai, W.C. Lin, D.D. Tang, and M.-J. Tsai, “The switching behaviors of submicron magnetic tunnel junctions with synthetic antiferromagnetic free layers,” J. Appl. Phys., vol. 97, pp. 10C923.1-10C923.3, May. 2005. [SCI, 2.26]

B. International Conference paper
1. (Invited) Chien-Chung Hung, M.J. Kao, W.C. Lin, S. Chao, D. Tang, and M.-J. Tsai, “Low writing current magnetoresistive random access memory (MRAM) with side metal pillar write word line (PWWL),” in Int. Symp. Advan. Magn. Tech. (ISAMT) Dig., Taipei, Nov. 13-16, 2003, p. 66.
2. Chine-Chung Hung, M.J. Kao, and M.-J. Tsai, “Magnetoresistive random access memory (MRAM) with low writing current,” in 2nd Annual Nano Mater. for Defense Applications Symp. (NMDAS), Maui, Feb. 19-26, 2004. (Poster paper)
3. Chien-Chung Hung, M.J. Kao, Y.S. Chen, Y.H. Wang, H.H. Hsu, C.M. Chen, Y.J. Lee, W.C. Chen, J.Y. Lee, W.S. Chen, W.C. Lin, K.H. Shen, J.H. Wei, L.C. Wang, K.L. Chen, S. Chao, D.D. Tang, and M.-J. Tsai, “High density and low power design of MRAM,” in IEEE Int. Electron Device Meeting (IEDM) Tech. Dig., San Francisco, Dec. 13-15, 2004, pp. 575-578. (Oral paper)
4. (Invited) Chien-Chung Hung, “High performance MRAM,” in 2nd Japan-Taiwan Workshop on Advanced Magn. Tech. (JTWAMT), Nagano, Sep. 19-22, 2005.
5. (Invited) Chien-Chung Hung, “Writing architecture for low power MRAM,” in Non-Volatile Memory Workshop, Hsinchu, Nov. 22-23, 2005.
6. Chien-Chung Hung, Y.S. Chen, D.Y. Wang, Y.J. Lee, W.C. Chen, Y.H. Wang, C.T. Yen, S.Y. Yang, K.H. Shen, C.P. Chang, C.S. Lin, K.L. Su, H.C. Cheng, Y.J. Wang, D.D.-L. Tang, M.-J. Tsai, and M.J. Kao, “Adjacent-reference and self-reference sensing scheme with novel orthogonal wiggle MRAM cell”, IEEE Int. Electron Device Meeting (IEDM), submitted, 2006.
7. D.S. Chao, Chien-Chung Hung, D.Y. Shu, M.-J. Kao, W.Y. Hsieh, M.-J. Tsai, Benson Wang, Bill Teng, H.P. Tsai, Rick Lin, and Max Chen, “Optimization and fabrication of planer edge termination techniques for a high breakdown voltage and low leakage current P-I-N diode,” in 19th Annual IEEE Appl. Power Electronics Conf. (APEC) and Exposition, Anaheim, Feb. 22-26, 2004, vol. 1, pp. 241-245. (Oral paper)
8. C.L. Su, R.F. Huang, C.W. Wu, Chien-Chung Hung, M.J. Kao, Y.J. Chang, and W.C. Wu, “MRAM defect analysis and fault modeling,” in IEEE Int. Test Conference (ITC), Charlotte, Oct. 26-28, 2004, pp. 124-133. (Oral paper)
9. Y.H. Wang, W.C. Chen, Y.H. Chen, K.H. Shen, Chien-Chung Hung, C.M. Chen, Y.J. Lee, T.G. Liao, H.H. Hsu, W.S. Chen, D.C. Liu, M.J. Kao, L.C. Wang, W.C. Lin, D.D. Tang, and M.-J. Tsai, “The study of switching behaviors in sub-micrometer magnetic tunnel junction using synthetic antiferromagnetic free layer,” in 49th Magn. Magn. Mater. (MMM) Conference, Jacksonville, Nov. 7-11, 2004, pp. 378. (Poster paper)
10. W.C. Chen, Y.H. Wang, Y.J. Lee, K.H. Shen, Y.H. Chen, Chien-Chung Hung, C.M. Chen, H.H. Hsu, M.J. Kao, L.C. Wang, W.C. Lin, D.D. Tang, and M.-J. Tsai, “Modification of interlayer coupling by adjusting synthetic antiferromagnetic free layers in magnetic tunnel junction,“ in 49th Magn. Magn. Mater. (MMM) Conference, Jacksonville, Nov. 7-11, 2004, pp. 34. (Poster paper)
11. (Invited) Y.S. Chen, W.C. Lin, C.M. Chen, Chien-Chung Hung, K.L. Chen, M.J. Kao, M.-J. Tsai, D.D. Tang, “Magnetic tunneling junction device model for circuit simulation,” in IEEE Int. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA-TECH), Hsinchu, April 25-27, 2005, pp. 78-81.
12. Y.J. Lee, Chien-Chung Hung, M.J. Kao, and M.-J. Tsai, “Thermal excitation effect on toggle switching in SAF free layer,” in 50th Magn. Magn. Mater. (MMM) Conference, San Jose, Oct. 30-Nov. 3, 2005, pp. 402. (Poster paper)
13. C.P. Chang, Chien-Chung Hung, Y.H. Wang, Y.J. Lee, K.L. Su, W.C. Chen, Y.H. Chen, C.S. Lin, M.J. Kao, J.F. Huang, and M.-J. Tsai, “Writing architecture for magnetic random access memory with negative pulse writing scheme,” in IEEE Int. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA-TECH), Hsinchu, April 24-26, 2006, pp. 44. (Oral paper)
14. C.L. Su, C.W. Tsai, C.W. Wu, Chien-Chung Hung, Y.S. Chen, and M.J. Kao, “Testing MRAM for write disturbance fault,” in IEEE Int. Test Conference (ITC), Santa Clara, Oct. 24-26, 2006, accepted. (Oral paper)
15. Y.J. Lee, Chien-Chung Hung, M.J. Kao, and M.-J. Tsai, “Yield loss in toggling MRAM at larger bias field,” in Int. Conference Magn. (ICM), Kyoto, Aug. 20-25, 2006, accepted. (Poster paper)
16. Y.J. Lee, Chien-Chung Hung, D.Y. Wang, K.H. Shen, D.D.-L. Tang, S. Chao, M.-J. Tsai, and M.J. Kao, “Study on the mechanism of yield loss of toggle MRAM at strong bias field,” in Asia-Pacific Data Storage Conference (APDSC’06), Hsinchu, Aug. 28-30, 2006, accepted. (Poster paper)

C. Local Conference paper
1. S. Chao and Chien-Chung Hung, “LiTaO3 鐵電矯頑電場之光敏現象及其在電場反轉準相位匹配二次諧波產生藍光雷射之應用”, in台灣光電科技研討會 (Photonics Taiwan ’96) Proceeding, Hsinchu, Dec. 12-13, 1996.
2. (Invited Speaker & Panelist) Chien-Chung Hung and M.J. Kao, “磁性記憶體技術的發展現況”, in台灣磁性技術協會 (TAMT) 年會暨第十六屆磁學與磁性技術研討會, Taipei, Aug. 20-22, 2003.
3. Chien-Chung Hung, K.H. Shen, Y.S. Chen, Y.H. Wang, M.J. Kao, and M.-J. Tsai, “High performance magneto-resistive random access memory (MRAM) ,” in 奈米國家型科技計畫 (Taiwan Nano Tech 2005) Proceeding, Taipei, Sep. 21-23, 2005. (成果發表)