本論文研究以改善16 nm鰭式電晶體均勻性與電性表現為主軸，主要調變閘極堆疊的沉積溫度與退火製程，並對電晶體做電性的分析與討論。研究成果可分為三部分如下。
第一部分，high-k沉積後退火處理之升溫條件對電晶體的影響。利用high-k沉積後的快速升降溫退火(Post Metal Annealing, PMA與Post Cap Annealing, PCA)調變來促進HfO2結成tetragonal或cubic晶相，進而提升電晶體的電容值與導通電流。對於sample在high-k沉積後只做PCA而言，相較於標準樣品，NFET與PFET的導通電流分別有3.55%與27.7%的提升、電容分別有21.17%與19.13%的提升。然而閘極電流增加超過一個order，此問題可再加上PMA製程來解決。
第二部分，金屬閘極之沉積溫度對電晶體均勻性的影響。藉由降低金屬閘極的沉積溫度，使晶粒變小，總晶粒數變多進而抑制Work Function Variation(WFV)，達到更佳的臨界電壓均勻。對於樣品沉積溫度300 °C而言，相較於沉積溫度380 °C，NFET與PFET的Vth標準差分別有35.27%與38.17%的顯著改善，同時漏電流也有35.70%與38.19%的下降。
第三部分，循環式沉積退火閘極氧化層對電晶體均勻性之影響。藉由循環式沉積退火的方式來成長閘極氧化層，減少隨機長晶的現象，進而提升電晶體Vth的均勻性。實驗結果發現，sample只做Post Deposition Annealing(PDA)有最小的Vth標準差，而sample做沉積-退火-沉積-退火(DADA)則稍微大一點。但對於sample DADA，相較於標準樣品，NFET與PFET之Vth標準差仍有27.62%與32.52%的改善。其不及sample PDA的原因為8 Å的厚度無法使high-k介電層均勻且有效地結晶。

The purpose of this thesis is to improve the uniformity and electrical properties of 16 nm FinFET by tuning the deposition temperatures and annealing conditions for gate stack. The experimental results consist of three parts as follows.
The first part is about effects of annealing temperature profile after high-k deposition on FinFET. The temperature spiking profile of annealing was applied to achieve a higher-k gate dielectric with more formation of tetragonal or cubic crystalline phase, which contributes to a higher drive current and capacitance. In comparison with the standard sample, the drive current of sample with only PCA increase 3.55% and 27.7% for NFET and PFET, respectively. The capacitance values of NFET and PFET also increase 21.17% and 19.13%, respectively. However, the gate current of sample with PCA increases more than one order, which can be resolved by an additional PMA process.
The second part is about effects of deposition temperature of metal gate on Vth uniformity of FinFET. A lower deposition temperature of metal gate was applied to decrease the grain size and increase the total number of grains, which lowers work function variation(WFV) and achieves better Vth uniformity. As compared to the sample with deposition temperature at 380 °C, Vth variance of sample with deposititon temperature at 300 °C significantly improve 35.27% and 38.17%; meanwhile, off currents also decrease with 35.70% and 38.19% for NFET and PFET, respectively.
The third part is about effects of cyclical deposition and annealing of gate dielectric on Vth uniformity of FinFET. Random grain crystallization can be reduced by forming gate dielectric with cyclical deposition and annealing, which achives better uniformity of Vth. Results show that the Vth variance of sample with post deposition annealing(PDA) is the smallest and that with Dep-Anneal-Dep-Anneal(DADA) is a little larger. However, in comparison with standard sample, the Vth variance of sample with DADA still can be reduced with 27.62% and 32.52% for NFET and PFET, respectively. The reason why the Vth variance of sample with DADA is larger than that with PDA may be because a 0.8 nm thick high-k dielectric cannot be uniformly and effectively crystalized.

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