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研究生: 蘇育玠
Su, Yu-Jay
論文名稱: 適用於寬頻毫米波系統之混合式預編碼多輸入多輸出濾波正交分頻多工基頻處理器
Hybrid-Precoding-Based MIMO Filtered-OFDM Baseband Processor for Wideband Millimeter Wave Systems
指導教授: 黃元豪
Huang, Yuan-Hao
口試委員: 蔡佩芸
Tsai, Pei-Yun
伍紹勳
Wu, Sau-Hsuan
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 109
語文別: 英文
論文頁數: 69
中文關鍵詞: 寬頻毫米波混合式預編碼多輸入多輸出濾波正交分頻多工基頻處理器
外文關鍵詞: Wideband, Millimeter-Wave, Hybrid-Precoding, MIMO, Filtered-OFDM, Baseband, Processor
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  • 高吞吐量傳輸可以通過多輸入多輸出毫米波系統來達成。然而,在全數位多輸入多輸出系統中,數據轉換器和射頻鏈使用了許多硬體元件。因此,我們利用混合預編碼架構來減少數據轉換器和射頻鏈的硬體浪費。
    另一方面,引入濾波後的正交分頻多工技術來滿足未來無線通訊系統的需求,該無線通訊系統具有比傳統正交分頻多工技術更高的效能。過濾式正交分頻多工技術是一種依照各個子帶過濾的方法,因為整個頻寬被劃分為多個單獨的子帶,每個子帶分別承載相應的數據訊息。
    本文提出了一種基於混合預編碼的多輸入多輸出濾波正交分頻多工基頻處理器,該處理器利用了單輸入單輸出濾波正交分頻多工技術,重新設計了適合多輸入多輸出架構的通道估測方法。利用正確的多輸入多輸出通道狀態資訊,可以將混合預編碼應用於多輸入多輸出濾波正交分頻多工,以解決關於頻率選擇性寬頻通道的問題。


    The high-throughput transmission can be provided by the multiple-input and multipleoutput (MIMO) millimeter wave (mmWave) system. Nevertheless, in the fully-digital
    MIMO system, a lot of hardware component are adopted by the data converters and
    RF chains. Therefore, we utilize the hybrid precoding to cut down the hardware waste
    of data converters and RF chains. On the other hand, filtered-OFDM was introduced
    to fulfill the requirement of the wireless communication system in the future which has
    a higher performance than the conventional OFDM. Filtered-OFDM is a per subband
    filtering method as the entire bandwidth is partitioned into separate subbands each
    carrying respective data information. In this thesis, we propose the Hybrid-PrecodingBased MIMO Filtered-OFDM Baseband Processor which take advantage of the SISO
    filtered-OFDM and redesign the channel estimation method that can be suitable to the
    MIMO architecture. With the correct MIMO channel state information, the hybrid
    precoding can be applied to MIMO filtered-OFDM to solve the issue about frequency
    selective wideband channel.

    1 Introduction 1 1.1 Filtered-OFDM MIMO Systems . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Hybrid Precoding Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Research Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Hybrid Precoding and Filtered-OFDM 5 2.1 Channel Model of Millimeter Wave MIMO Systems . . . . . . . . . . . . 5 2.1.1 Narrow-band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.2 Wide-band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Hybrid Precoding in OFDM Systems [1] . . . . . . . . . . . . . . . . . . 8 2.2.1 Successive Interference Cancellation with Matrix-Inversion Bypass (SIC-MIB) Analog Precoding and Combining Algorithm . . . . . 11 2.2.2 Block SVD Power Method Baseband Precoding Algorithm . . . . 17 2.2.3 Square Root Baseband Combining Algorithm . . . . . . . . . . . 20 2.3 Filtered Orthogonal Frequency Division Multiplexing [2] . . . . . . . . . 23 2.3.1 OFDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.2 Upsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.3 Filter Algorithms for Spectral Con_nement . . . . . . . . . . . . . 30 2.3.4 Frequency Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ii CONTENTS 2.3.5 Frequency Shift in Receiver and Downsampling . . . . . . . . . . 37 2.3.6 Frame Synchronization Algorithm . . . . . . . . . . . . . . . . . . 38 2.3.7 Channel Estimation Algorithm . . . . . . . . . . . . . . . . . . . 41 3 Proposed Baseband Processor for Hybrid-Precoding-Based MIMO Filtered- OFDM Systems 45 3.1 Algorithms for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 Algorithms for Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3 Channel Estimation for Baseband Precoder and Combiner . . . . . . . . 48 3.4 Speci_cation and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 Hardware Architecture and Simulation Results 55 4.1 Baseband Processor Architecture . . . . . . . . . . . . . . . . . . . . . . 56 4.2 Timing Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3 Fixed-point Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.4 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5 Conclusion 65 References 67

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