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研究生: 吳岱穎
Wu, Dai-Ying
論文名稱: 具有電容不匹配校正之 2.4 GHz數位控制震盪器
A 2.4-GHz Digitally Controlled Oscillator with Capacitance Mismatch Calibration
指導教授: 謝志成
Hsieh, Chih-Cheng
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 106
中文關鍵詞: 震盪器數位校正
外文關鍵詞: oscillator, digital, calibrate
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  • 摘要

      本論文為設計一個應用於 2.4 GHz 工業╱科學╱醫療之2.4 GHz 頻段數位控制震盪器。由於我們在電路的設計階段無法預測在實際的操作裡,來自於實體電路的製作、電路的工作電壓和每一次工作環境 (PVT)總共會貢獻多少變化量。,此不確定因素使得操作於開迴路之震盪器不適用於許多應用裝置上。為消除以上的缺點限制,在此論文裡提出一個具有校正不匹配效應能力之數位控制震盪器。

      此論文所提出的架構包括一個數位控制震盪器、一個能擷取震盪器頻率資訊的計數器、電容不匹配量化計算器及校正後震盪器控制碼產生器。在此震盪器裡我們使用對電容做開關的方式來當作電路裡的可變電容,使得震盪器訊號較能抵抗來自於類比雜訊干擾的操作環境。計數器負責將我們震盪器的震盪頻率回饋給電容不匹配量化計算器以用於得知多少誤差存在於我們的被控制單元。當得到足夠的誤差資訊後,控制碼產生器則能依照此資訊來產生對應於使用者所需之震盪訊號的校正後控制碼來調控此電路的震盪器。

      此論文的電路設計將實現於台灣積體電路製造股份有限公司所提供的互補式金屬氧化層半導體 0.18 微米製程。全部的總電路大小是 1 × 1 平方毫米。從量測結果顯示,此震盪器的震盪範圍約為 2.28 ~ 2.42 GHz。在距離載波500 kHz之相位雜訊能量低於載波能量 101 dB。此數位控制震盪器所能提供的解析度大約是七個控制碼,消耗的功率約為 13 毫瓦。


    Abstract

    In this thesis, a digitally controlled oscillator (DCO) designed for 2.4 GHz Industrial, Science, and Medical band (ISM-band) application is proposed. As the non-ideal effects due to process, supply voltage and temperature (PVT) variations, the DCO is not ideally controlled. This makes DCO open-loop operation unsuitable for most applications. By applying capacitance mismatch calibration, it is possible to accurately control the DCO frequency. Therefore, the above limit no longer exists.

    The proposed design consists of a digital controlled oscillator (DCO), a ripple counter, a mismatch calculator and a calibrated code generator. By adopting switched-capacitor arrays as varactor, the DCO oscillation frequency is stable and robust against analog noise. The counter estimates this oscillation frequency and feedback it to the mismatch calculator to find the capacitance variation. After variation values are obtained, the calibrated code generator could transfer the desired oscillation frequency into a best-fitted DCO control code.

    This design is implemented in TSMC 0.18 μm 1P6M CMOS process and the chip area is 1 × 1 mm2. According to the measurement results, the oscillating frequency is 2.28 ~ 2.42 GHz with total 140 MHz tuning range. The phase noise at 500-kHz frequency offset is less than -101 dBc/Hz. The frequency resolution is about 7 bits and the total power consumption is about 13 mW from an 1.8-V power supply.

    Contents Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 Thesis Organization 5 Chapter 2 Architecture 7 2.1 Introduction 7 2.2 Design Specification of Digitally Controlled Oscillator 8 2.2.1 Frequency Band and Resolution 8 2.2.2 Phase Noise 10 2.2.3 Proposed Specification 12 2.3 Digitally Controlled Oscillator (DCO) Architecture 13 2.3.1 Non-ideal Effect in DCO 13 2.3.2 DCO Architecture with Capacitance Mismatch Calibration Ability 16 2.4 Summary 18 Chapter 3 Digitally Controlled Oscillator 19 3.1 LC-Type Digitally Controlled Oscillator 19 3.1.1 LC Tank Oscillator Overview 19 3.1.2 Negative Resistance Circuit 22 3.1.3 Switch-Capacitor Array 25 3.1.4 TSMC Spiral Inductor 30 3.2 Full-Swing Buffer 31 3.3 Current Bias Circuit 37 3.4 Simulation Results 39 3.5 Summary 53 Chapter 4 Digital Calibration Loop 54 4.1 Capacitance Mismatch Calculation 55 4.1.1 Algorithm of Mismatch Calculation 56 4.1.2 Logic Implement 62 4.2 DCO Calibrated Code Generation 75 4.2.1 Algorithm of Code Generation 75 4.2.2 Logic Implement 80 4.3 Summary 82 Chapter 5 Chip Implementation and Measurement Results 83 5.1 Mixed-Mode Simulation 83 5.2 Chip Measurement 87 5.2.1 Measurement setup 87 5.2.2 Measurement Result 90 5.2.3 Measurement discussion 102 5.3 Summary 104 Chapter 6 Conclusion and Future Work 105 6.1 Conclusion 105 6.2 Future work 106

    Reference

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