為了持續元件微縮並提高元件效能，許多新穎的研究成果已被發表出來，其中，高功函數金屬閘極的研究相當引人注目。本研究提出兩種以MoN為主，搭配TiN薄膜的堆疊式金屬閘極，分別為TM_0與TMT_100閘極，從實驗結果發現，其功函數均較單層MoN閘極高，並在多項電特性表現上較MoN單層閘極優良。對TM_0與TMT_100閘極施以不同的退火溫度，深入探討閘極的熱穩定性與元件可靠性，根據實驗結果發現，TM_0經過PMA 950oC後，在可靠性方面的表現最佳。兩種gate stack的功函數熱穩定性均較單層MoN好。
本研究中第三種gate stack為TMT_20，調變閘極底層TiN為2nm的結果，大幅提升了三層式閘極在高溫的可靠度與元件熱穩定性。
本研究將三種以MoN及TiN為主，不同結構的金屬閘極與high-k介電層HfAlO整合應用。發現TM_0閘極在多項電特性上的表現均最優，且其在HfAlO上的可靠性較其在SiO2上更優。最後，本研究將TM_0搭配以ALD沉積不同濃度的HfAlO介電層做整合。發現最佳化的HfAlO介電層濃度為Hf13.24Al18.11O68.65，其有效功函數為5.00eV。比較TM_0閘極在以MOCVD與ALD沉積之HfAlO介電層上的特性，發現ALD formed Hf13.24Al18.11O68.65介電層展現了與TM_0閘極最佳化的元件電特性，以及優秀的high-k & metal gate整合效果。

[1] M. S. Krishinan, et al., IEDM, p. 571, 1998
[2] You-Seok Suh et al., “Electrical Characteristics of TaSixNy Gate Electrodes For Dual Gate Si-CMOS Devices,” Symposium on VLSl Technology Digest of Technical Papers, p.47, 2001
[3] Stefan De Gendt, IEDM Short Course, IMEC., 2004
[4] Q. Lu, et al., IEEE Symp. On VLSI Technology Tech. Dig., p.49, 2001
[5] Y. C. Yeo, et al., IEEE Electron Device Lett., vol.22, p.227, 2001
[6] Seiichiro Kawamura, IEEE Custom Integrated Circuits Conference, pp.467-474, 2002
[7] B. Travel et al., IEDM, p.825, 2001
[8] Q. Xing et al., VLSI, p.101, 2003
[9] H. Zhong, et al., IEDM Tech. Dig., p.467, 2001
[10] I. Polishchuk, et al., IEEE Electron Device Lett., vol.22, p.444, 2001
[11] C. Hobbs, et al., IEEE Symp. On VLSI Technology Tech. Dig., 2-1. 2003
[12] C. Wang, et al., Appl. Phys. Lett., vol.83 (2), p.308, 2003
[13] C. Hobbs, et al., IEEE Electron Device Lett., vol.51(6), pp.971, 2004
[14] C. Hobbs, et al., IEEE Electron Device Lett., vol.51(6), pp.978, 2004
[15] Mark Rodder, IEDM Short Course, Texas Instrument, 2004
[16] H. Ono, et al., Appl. Phys. Lett., vol.73, no.11, p.1517, 1998
[17] R. Beyers, J. of Appl. Phys., vol.56, p.1, 1984
[18] V. Misra, et al., MRS bulletin, vol.27, no.3, p.212, 2002
[19] C. Wang, et al., Appl. Phys. Lett., vol.83 (2), pp.308, 2003
[20] W. Zhu, et al., IEEE Electron Device Lett., vol.51 (1), pp.98, 2004
[21] M. V. Fischetti, et al., J. Appl. Phys., vol.90 (9), p.4587, 2001
[22] Robert Chau, et al., IEEE Electron Device Lett., vol.25 (6), p.408, 2004
[23]張新君，“金氧半元件金屬閘極和高介電係數電層之製程整合研究”，國立清華大學工程與系統科學系，2006
[24] Tsu-Jae King et al., Novel Materials and Processes for MOS Devices final report: MICRO Project 98-071, 1998-99
[25] P. Ranade et al., Electrochem. & Sol-State Lett., 5, p. G85, 2001.
[26] Bing-Yue Tsui et al., Journal of The Electrochemical Society, 153 3 G197-G202, 2006
[27] J. R. Hauser and K. Ahmed, "Characterization of ultrathin oxides using electrical C-V and I–V measurement," Characterization Metrology ULSI Technology, pp. 235–230, 1998
[28] S. Zafar et al., Apply Phys. Letter, vol. 80, pp. 4858-4860, 2002.
[29] Huang-Chun Wen et al., IEEE Electron Device Lett., vol.27, no.7 pp.598-601, July 2006
[30] Po-Yen. Chien, “Integration of electrical characteristics for MOS devices with Molybdenum metal gate”, thesis in the Department of Engineering and System Science NTHU, 2007
[31] D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed., John Wiley & Sons, New York, 1998
[32] Y. Nishi, et al., Handbook of Semiconductor Manufacturing Technology, Chap.28, Marcel Dekker, New York, 2000
[33] N. V. Nguyen, et al., Appl. Phys. Lett., 77, 3012, 2000
[34] P. T. Gao, et al., Thin Solid Films, 377, 557, 2000
[35] K. Kukli, et al., Thin Solid Films, 260, 135, 1995
[36] M. Cassir, et al., Appl. Surf. Sci., 193, 120, 2002
[37] C. M. Perkins, et al., Appl. Phys. Lett., 78, 2357, 2001
[38] C. Chaneliere, et al., Microelectron. Reliab., 39, 261, 1999
[39] D. D. L. Chung, et al., X-Ray Diffraction at Elevated Temperatures: A Method for In-Situ Process Analysis, Chap.1, VCH Publishers, New York, 1993
[40] Powder Diffraction File: Inorganic and Organic Data Book, PDF#19-1299, 25-0922, 25-1257, 25-1366, 27-1402, 34-1084, 42-0060, 42-1120, and 72-1088, JCPDS – International Center for Diffraction Data, American Society for Testing and Materials, Swarthmore, PA, 1950-2003
[41] K. Onishi, et al., Symp. VLSI Tech., p.131, 2001
[42] Stanley Wolf, Silicon Processing for the VLSI ERA, vol.2, Lattice Press, California, 1990
[43] Tohru Hara, Taira Kitamura, Masaru Tanaka, Takuya Kobayashi, Keizo Sakiyama, Shigeo Onishi, Kazuya Ishihara, Jun Kudo, Vukihiro Kino, and Noboru Yamashita , "Barrier Effect of TaSiN Layer for Oxygen Diffusion," J. Electrochem. Soc., Vol. 143, no. 11, pp. L264-L266, 1996
[44] Yasushi Akasaka et al., Japanese Journal of Applied Physics Vol. 45, No. 4B, pp. 2933–2938, 2006
[45] X.Sun et al., Thin Solid Film, vol.236, p. no1/2, Dec. 1993
[46] Heiji Watanabe, et al., APL 85, p.449, 2004
[47] H. B. Michaelson, J. Appl. Phys., vol.48, p.4729, 1977
[48] Tzung-Lin Li et al., IEEE Transactions on Electron Devices, VOL. 53, NO. 6, pp.1420-1426, June 2006
[49] R. Nieh, et al., IWGI, p.70, 2001
[50] C. H. Lee, et al., IEDM Tech. Dig., p.27, 2000
[51] B. H. Lee, et al., IEDM Tech. Dig., p39, 2000
[52] R. Choi, et al., Symp. VLSI Tech., p.15, 2001
[53] V. Mikhelashvili, et al., IEEE Electron Device Lett., 27, p.344, 2006.
[54] Paul E. Nicollian, et al., in IRPS, pp.400-404, 1999
[55]莊惠淇，“利用閘堆疊式介電層及界面工程加強金氧半元件電性之研究”，國立清華大學工程與系統科學系，2007
[56] H. Y. Yu, et al., IEEE Electron Device Lett., vol.25, pp.337-339, 2004
[57] Jaehyun Kim and Kijung Yung, ECS, 152 (10) F153-155, 2005
[58] Ping-Hung Tsai et al., IEEE Electron Device Lett., VOL. 29, NO. 3, pp.265-268, March 2008
[59] S. H. Bae et al., IEEE Electron Device Lett., VOL. 24, NO. 9, September 2003
[60] H. Z. Massoud, “Charge transfer dipole moments at the Si-Si02 interface,” J. Appl. Phys., vol63 (no. 6), pp.2000-5, March 1988
[61] R. C. Keller and C. R. Helms, J. Yuc. Sci. Tech. A, vol 10 (no. 4), pp.775-80, July/Aug 1992
[62] Rashmi Jha et al., APL, 87 223503, 2005
[63] Jiang Lu, et al., J. Vac. Sci. Technol. B, vol. 24, No. 1, pp.349-357, Jan/Feb 2006