奈米級NAND型氮化物儲存快閃記憶體技術之研究

簡易檢索 / 詳目顯示

回結果列表

研究生：	徐子軒 Hsu, Tzu-Hsuan
論文名稱：	奈米級NAND型氮化物儲存快閃記憶體技術之研究 A Study on Nano-Scale SONOS-Type NAND Flash Memory Technologies
指導教授：	金雅琴 King, Ya-Chin
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	112
中文關鍵詞：	快閃記憶體、氮化物電荷儲存、不均勻的電場分佈
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文對於SONOS-type氮化物電荷儲存NAND型快閃記憶體元件作深入的探討。首先，分析SONOS 和BE-SONOS結構的本質特性，發現SONOS (底層氧化層>40A) 的抹除機制是一種電子由缺陷跳脫的行為，BE-SONOS是以通道電洞注入的方式來抹除所儲存的電荷。由於此有效率的抹除方式，BE-SONOS呈現快速的抹除速度和較佳的重複寫入抹除次數。
另一方面，對不同的STI結構對SONOS-type快閃記憶體電特性所造成的影響，進行分析討論。藉由量測及模擬之特性發現，此效應主要因為元件上不均勻的電場分佈，造成寫入和抹除後電荷分布的不均勻。藉由寫入抹除過程中量測元件的gm和Sw變化行為及TCAD三維模擬下寫入抹除過程中電流和電場變化的暫態分析，以佐證所提出之理論模型。一種新型的body-tied FinFET BE-SONOS結構也在本論文首次提出；此結構利用電場局部增強效應以實現高速操作的NAND快閃記憶體。
相對於傳統NAND型快閃記憶體採用FN穿透機制來做寫入和抹除的動作，本論文提出了一種新的基板暫態熱載子注入機制來作為寫入和抹除的方式。這項新穎的操作機制可用較低電壓完成寫入和抹除的動作，並能於記憶體陣列中隨意進行讀取、寫入及抹除的動作，適用於編碼型(code)和資料儲存型(data)快閃記憶體的應用。

Contents
Abstract (Chinese)…………………………I
Abstract (English)…………………………II
Acknowledgement (Chinese)…………………IV
Contents…………………………………………V
List of Tables……………………………………………………………...IX
List of Figures…………………………………………………………….…X

Chapter 1  Introduction……….…………………………………..………1
1.1    Background and Motivation………...…………..……………..………………..1
1.2    Thesis Organization………………..…………………………………………….3

Chapter 2  Review of Flash Memories.………………….…..…..………4
2.1    Solid-State Memory………...……………………………………………………4
2.2    Nonvolatile Memory………….………………………………………………….5
2.2.1    Evolution of Flash Memory……...……………….……………………….5
2.2.2    What is Flash Memory ?…..……….………………………..…………..5
2.2.3    Main Stream of Flash Memory…………….……………………………..6
2.2.4    Scaling Challenges of Floating Gate NAND Flash Memory…...……..8
2.2.5    Charge-Trapping Flash Memory………….…...……….……….…..10
2.2.6    SONOS-Type NAND Flash Memory……….………………..………11
2.2.7    Hot carrier mode NAND Flash Memory………………………………13
2.3    Summary………………………………………………………………………...14

Chapter 3 Intrinsic Study of SONOS and Bandgap Engineered (BE)-SONOS……………………..……………………………..……..24
3.1    Introduction…………….…………………………………………………….…24
3.2    Sample and Experiment Description………………………………………...25
3.3    Program Characteristics (ISPP)………………………..…………………….25
3.4    Erase Characteristics…………………………………….……………………..28
3.5    Endurance Property…………………………………..………………..….…30
3.6    Read Disturbance and Data Retention……………….……………………….30
3.7    Summary…………………..…………………………………………………..31

Chapter 4  Local Trapping and Edge Effect in SONOS-Type NAND Flash Device ..……………..………………….……..……………..………41
4.1    Introduction………………………….…..…………………………….…….41
4.2    Sample Description…………………………….…….……………………….42
4.3    Electric Field Analysis…………………………..…………….……………42
4.4    Effects on Program/Erase Characteristics.…………………….…………43
4.5    Read Disturb Comparison…………………………………………………45
4.6    Retention Characteristics…………...……………………………………..…46
4.7    Summary……………………………..………………………………………….47

Chapter 5  High-Speed Rounded Tip Body-Tied FinFET BE-SONOS NAND Flash …..……………….……….……………...………………57
5.1    Introduction…………………………….………………………..……………57
5.2    Sample Preparation and Experimental Setup……………..………………….57
5.3    Theoretical Model………………………….…………………………………58
5.4    Cell Characteristics and Field Enhancement Factor Extraction……...…….60
5.5    Non-uniform Injection Effect..…………………………..………………….62
5.6    MLC NAND Flash Application…………………..………………………..64
5.7    Summary……………………………………..……………….………………66

Chapter 6 Channel-Program-Erase Technique with Substrate Hot Carrier Injection for SONOS-Type NAND Application………………82
6.1     Introduction………………………….…………..…..……..……………..82
6.2    Experimental Description………………………………………………….83
6.3    Results and Discussion………………………………………………………..84
6.4    Divided-Substrate-Bit-Line (DSB-NAND) Application………..…………86
6.5    Summary…………………………………………………………………….88

Chapter 7  Conclusions…………………….......................…………98

Appendix…………………….………………………..…………………..100
A: Explanation of the Theoretical Derivation of Eqs. (1-2)……..…….…….100
Reference…………………….………………………..…………………..102
Publication List………….………………………..…………………..110

                                

[1] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, p. 1288, 1967
[2] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connel, and R. E. Oleksiak, ” The variable threshold transistor, a new electrically alterable, non-destructive read-only storage device, ” IEEE IEDM Tech.,1967.
[3] C. Hu, ”Lucky electron model of hot electron emission, ” IEEE IEDM Tech. Dig., p.22,1979.
[4] S.Aritome et al., “Reliability issues of Flash memory cell,” Proc. IEEE, vol.81,no. 5,pp. 776-788, 1993.
[5] K.D. Suh, B.H. Suh, Y.H. Lim, J.K. Kim, Y.J. Choi, Y.N. Koh, S.S. Lee, S.C. Kwon, B.S. Choi, J.S. Yum, J.H. Choi, J.R. Kim, and H.K. Lim, “A 3.3V 32Mb NANF Flash memory with incremental step pulse programming scheme”, IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, 1995.
[6] K. Imamiya, Y. Iwata, Y. Sugiura, H. Nakamura, H. Oodaira, M. Momodomi, Y. Itoh, T. Watanabe, H. Araki, K. Masuda, and J. Miyamoto, “A 35ns-Cycle-Time 3.3V-Only 32Mb NAND Flash EEPROM,” ISSCC Dig. Tech. Papers, pp. 130-131, Feb. 1995.
[7] F. Arai, T. Maruyama, R. Shirota,” Extended data retention process technology for highly reliable flash EEPROMs of 106 to 107 W/E cycles”, Proc. IRPS, p. 378-382, 1998.
[8] M. Ichige, Y. Takeuchi, K. Sugimae, A. Sato, M. Matsui, T. Kamigaichi, H. Kutsukake, Y. Ishibashi, M. Saito, S. Mori, H. Meguro, S. Miyazaki, T. Miwa, S. Takahashi, T. Iguchi, N. Kawai, S. Tamon, N. Arai, H. Kamata, T. Minami, H. Iizuka, M. Higashitani, T. Pham, G. Hemink, M. Momodomi, R. Shirota, ” A novel self-aligned shallow trench isolation cell for 90 nm 4 Gbit NAND flash EEPROMs”, VLSI Dig. Tech. P. 89-90, 2003.
[9] F. Arai, ”Future Outlook of Floating Gate Flash Memory”, 2006 International Conference on Solid State Devices and Materials, pp.292-293, 2006.
[10] Kinam Kim, Jung Hyuk Choi, Jungdal Choi and Hong-Sik Jeong, ” The future prospect of nonvolatile memory”, 2005 IEEE VLSI-TSA International Symposium, pp. 88 - 94, 2005.
[11] G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo, M. Gely, D. Lafond and S. Deleonibus, “Impact of few electron phenomena on floating-gate memory reliability”, in IEDM Tech. Dig., 2004, pp. 877-880.
[12] B. Eitan, P.Pavan, I.Bloom, E.Aloni, A. Frommer and D. Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
[13] Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu and Chih Yuan Lu, “A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory”, 2007 IEEE VLSI-TSA International Symposium, pp. 16 - 17, 2007.
[14] Takeshi Ishida, Yutaka Okuyama, and Renichi Yamada, “Characterization of Charge Traps in Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) Structures for Embedded Flash Memories”, 2006 IEEE International Reliability Physics Symposium Proceedings, pp. 516-522, 2006.
[15] Yu-Wang and M.H. White “An analytical retention model for SONOS nonvolatile memory devices in the excess electron state,” Semiconductor Device Research Symposium, 2003 International, 10-12 Dec 2003, pp. 156 – 157.
[16] Chang Hyun Lee, Kyung In Choi, Myoung Kwan Cho, Yun Heub Song, Kyu Charn Park, and Kinam Kim, “A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-Giga Bit Flash Memories,” Tech. Digest 2003 International Electron Devices Meeting, pp. 26.5.1 - 26.5.4, 2003.
[17] Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, Yen-Hao Shih, Sheng-Chih Lai, Ling-Wu Yang, Kuang-Chao Chen, Joseph Ku, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” Tech. Digest 2005 International Electron Devices Meeting, pp. 547-550, 2005.
[18] Yoocheol Shin, Jungdal Choi, Changseok Kang, Changhyun Lee, Ki-Tae Park, Jang-Sik Lee, Jongsun Sel, Viena Kim, Byeongin Choi, Jaesung Sim, Dongchan Kim, Hag-ju Cho and Kinam Kim, “A Novel NAND-type MONOS Memory using 63nm Process Technology for Multi-Gigabit Flash EEPROMs,” Tech. Digest 2005 International Electron Devices Meeting, pp.13.6.1 – 13.6.4, 2005.
[19] Hang-Ting Lue, Szu-Yu Wang, Yi-Hsuan Hsiao, Erh-Kun Lai, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Rich Liu, and Chih Yuan Lu, “Reliability Model of Bandgap Engineered SONOS (BE-SONOS)”, Tech. Digest 2006 International Electron Devices Meeting, pp. 495-498, 2006.
[20] M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgtaf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications”, in VLSI Tech.Dig., PP244-245, June 2004.
[21] S. Kim et al., “Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage”,VLSI Symp. pp 104-105, 2006.
[22] J. R. Hwang et al., “20nm gate bulk-FinFET SONOS flash”, IEDM Tech Dig. pp 154 - 157, 2005.
[23] Y. J. Ahn et al., “SONOS-type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory”, VLSI Symp. pp 106-107, 2006.
[24] Se Hoon Lee, Jong Jin Lee, Jeong-Dong Choe, Eun Suk Cho, Young Joon Ahn, Won Hwang, Taeyong Kim, Woo-Jung Kim, Young-Bae Yoon, Donghoon Jang, *Jongryeol Yoo, **Dongdae Kim, Kyucharn Park, Donggun Park, and Byung-Il Ryu.” Improved post-cycling characteristic of FinFET NAND Flash”, Tech. Digest 2006 International Electron Devices Meeting, pp. 33-36, 2006.
[25] C.C. Yeh, W.J. Tsai, M.I. Liu, T.C. Lu, S.K. Cho, C.J. Lin, Tahui Wang, Sam Pan, and C.Y. Lu, “PHINES: a Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEEE IEDM Tech. Dig., pp. 37.4.1-37.4.4, 2002.
[26] S. Shukuri, N. Ajika, M. Mihara,K. Kobayashi, T. Endoh, M. Nakashima, ” A 60nm NOR Flash Memory Cell Technology Utilizing Back Bias Assisted Band-to-Band Tunneling Induced Hot-Electron Injection (B4-Flash)”, VLSI Symposia on Technology, pp. 15-16, 2006.
[27] Szu-Yu Wang, Hang-Ting Lue, Erh-Kun Lai, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Jeng Gong, Kuang-Yeu Hsieh, Rich Liu, and Chih Yuan Lu, “Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory”, 2007 IEEE International Reliability Physics Symposium Proceedings, pp. 171-176, 2007.
[28] Hang-Ting Lue, Tzu-Hsuan Hsu, Szu-Yu Wang, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “Study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash” International Reliability Physics Symposium, IRPS 2008. April 27 Page:693 – 694.
[29] Hang-Ting Lue, Yen-Hao Shih, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A transient analysis method to characterize the trap vertical location in nitride-trapping devices,” IEEE Electron Device Lett, Vol. 25, No. 12, pp. 816-818, 2004.
[30] Hang-Ting Lue, Sheng-Chih Lai, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, Pei-Ying Du, Szu-Yu Wang, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, ”A Critical Review of Charge-Trapping NAND Flash Devices” ICSICT 2008, session D1.
[31] H- T. Lue, Y.H. Shih, K.Y. Hsieh, R. Liu, and C.Y. Lu, “Novel Soft Erase and Re-fill Methods for a P+-poly Gate Nitride-trapping Nonvolatile Memory Device with Excellent Endurance and Retention Properties”, IEEE 43rd Annual International Reliability Physics Symposium, pp.168-174, 2005.
[32] Y-Wang and M.H. White “Charge retention of scaled SONOS non-volatile memory devices at elevated temperatures,” Solid-State Electronic, vol.44, pp. 949-958, 2000.
[33] Tzu-Hsuan Hsu, Hang-Ting Lue, Sheng-Chih Lai, Ya-Chin King,, Kuang-Yeu Hsieh, Rich Liu and Chih Yuan Lu, “Reliability of Planar and FinFET SONOS Devices for NAND Flash Applications—Field Enhancement vs. Barrier Engineering”, 2009 IEEE VLSI-TSA International Symposium, to be published, 2009.
[34] Tzu-Hsuan Hsu, Hang-Ting Lue, Wu-Chin Peng, Ya-Chin King, Chia-Wei Wu, Szu-Yu Wang, Ming-Tsung Wu, Shih-Ping Hong, Jung-Yu Hsieh, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET”, Tech. Digest 2007 International Electron Devices Meeting IEDM, pp. 913-916, 2007.
[35] M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgtaf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications”, in VLSI Tech.Dig., PP244-245, June 2004.
[36] S. K. Sung, T. Y. Kim, E. S. Cho, H. J. Cho, B. Y. Choi, C. W. Oh, B. G. Cho, C. H. Lee and D. Park, “Fully Integrated SONOS Flash Memory Cell Array with BT-FinFET Structure”, in IEEE Silicon Nanoworkshop, pp. 102-103, 2005.
[37] C. Friederich, M. Specht, T. Lutz, F. Hofmann, L. Dreeskornfeld, W. Webber, J. Kretz, T. Melde, W. Rosner, E. Landgraf, J. Hartwich, M. Stadele, L. Risch and D. Richter “Multilevel p+ tri-gate SONOS NAND string arrays”, Tech. Digest 2006 International Electron Devices Meeting, pp. 963-966, 2006.
[38] K. H. Yeo, K. H. Cho, M. Li, S.D. Suk, Y. Y. Yeoh, M.S. Kim, H. Bae, J.M. Lee, S.K. Sung, J. Seo, B. Park, D. W. Kim, D. Park, and W. S. Lee, “Gate-all-around single silicon nanowire MOSFET with 7nm width for SONOS NAND Flash memory”, VLSI Symposia on Technology, session, pp. 138-139, 2008.
[39] E.K. Lai, H.T. Lue, Y.H. Hsiao, J.Y. Hsieh, C.P. Lu, S.Y. Wang, L.W. Yang, T. Yang, K.C. Chen, J. Gong, K.Y. Hsieh, R. Liu, and C.Y. Lu, “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, International Electron Device Meeting (IEDM), session 2-4, pp. 41-44, 2006.
[40] H.T. Lue, T.H. Hsu, S.Y. Wang, Y.H. Hsiao, E.K. Lai, L.W. Yang, T. Yang, K.C. Chen, K.Y. Hsieh, R. Liu, and C.Y. Lu, “Study of Local Trapping and STI Edge Effects on Charge-Trapping NAND Flash”, Tech. Digest 2007International Electron Devices Meeting, pp. 161-164, 2007.
[41] Peiqi.Xuan, Min. She, Bruce. Harteneck, Alex. Liddle, Jeffrey. Bokor, and Tsu-Jae King, “FinFET SONOS Flash Memory for Embedded Application”, Tech. Digest 2003 International Electron Devices Meeting, pp. 609-612, 2003.
[42] Tzu-Hsuan Hsu, Hang-Ting Lue, Ya-Chin King, Yi-Hsuan Hsiao, Sheng-Chih Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, ”Physical Model of The Field-Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices” IEEE Transaction on Electron Devices 2009, vol.56, pp.1235-1242, 2009.
[43] P.Y. Du, H.T. Lue, S.Y. Wang, T.Y. Huang, K.Y. Hsieh, R. Liu, and C.Y. Lu, “A Study of Gate-Sensing and Channel-Sensing (GSCS) Transient Analysis Method: Part II: Study of the Intra-Nitride Behaviors and Reliability of SONOS-type Devices”, IEEE Trans. Electron Devices, pp. 2229-2237, 2008.
[44] Y. Shin, J. Choi, C. Kang, C. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. j. Cho and Kinam Kim, “A Novel NAND-type MONOS Memory Using 63nm Process Technology for Multi-gigabit Flash EEPROMs”, Tech. Digest 2005 International Electron Devices Meeting, pp. 337-340, 2005.
[45] Sheng-Chih Lai, Hang-Ting Lue, Jung-Yu Hsieh, Ming-Jui Yang, Yan-Kai Chiou, Chia-Wei Wu, Tai-Bor Wu, Guang-Li Luo, Chao-Hsin Chien, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu and Chih-Yuan Lu, “A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices”, 2007 IEEE VLSI-TSA International Symposium, pp. 14 - 15, 2007.
[46] J.P. Colinge, L. Floyd, A. J. Quinn, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, K. Schruefer “Temperature Effects on Trigate SOI MOSFETs”, Electron Device Letter 2006 vol. 27, pp.172-174, 2006.
[47] Jae Sung Sim, et al. ” BAVI-Cell: A Novel High-Speed 50nm SONOS Memory with Band -to-band Tunneling Initiated Avalanche Injection Mechanism” in VLSI Tech. Dig., pp. 122-123, 2005.
[48] M. K. Cho and D.M. Kim,” Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EEPROM cells,” IEEE Electron Device Lett., Vol. 24 , pp. 260 – 262, Sep. 2003.
[49] Tzu-Hsuan Hsu, Ya-Chin King, Jau-Yi Wu, Hang-Ting Lue, Yen-Hao Shih, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A Novel Channel-Program-Erase Technique with Substrate Transient Hot Carrier Injection for SONOS NAND Flash Application” Solid-State Electronics, 2007. pp. 1523-1528.
[50] Tzu-Hsuan Hsu, Jau-Yi Wu, Ya-Chin King, Hang-Ting Lue, Yen-Hao Shih, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu, Chih-Yuan Lu, “A Novel Channel-Program-Erase Technique with Substrate Transient Hot Carrier Injection for SONOS Memory Application” Solid-State Device Research Conference, ESSDERC 2006. Proceeding of the 36th European, pp. 222-225, 2006.
[51] C.-N.B. Li, et al. “A novel Uniform-Channel-Program Erase (UCPE) flash EEPROM using an isolated P-well structure”, IEEE IEDM Tech. Digest, Page(s):779 – 782, 2000.
[52] Yen Hao Shih, et al. “Highly reliable 2-bit/cell Nitride Trapping Flash Memory Using a Novel Array-Nitride-Sealing (ANS) ONO Process ”, IEEE IEDM Tech. Digest, Page(s):559- 562, 2005.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文