覆晶構裝具有密度高、訊號傳輸速度快、電感低以及散熱處理容易等優點，而成為近代絕佳的構裝技術。覆晶式構裝之針測程序主要可分為「Probe-before-bump」與「Probe-after-bump」兩種。「Probe-after-bump」針測過程不會刮損焊墊表面，因此有較佳之凸塊下金屬(UBM)階梯覆蓋能力，但卻會延遲對晶圓良率之回饋以及晶圓良率偏低之責任歸屬問題；「Probe-before-bump」針測卡之針尖直接與焊墊接觸，可能會造成不良之UBM階梯覆蓋性及空孔產生，導致微電子元件之壽命降低並加速電子遷移效應等潛在問題。本研究首先介紹主要的針測與錫鉛凸塊製程技術，並提出一套數學解析法來預測「Probe-before-bump」之針測壓痕深度，然後以有限元素法及針測實驗來加以驗證。依據數學解析法，可求得「Probe-before-bump」較適當之針測卡及針測條件，以確保針測後覆晶結構之可靠性。本研究並利用深度感測奈米壓痕實驗，來獲得微電子元件薄膜結構之材料性質，並應用於數學解析法求得針測壓痕之深度。溫度與電流密度為影響電子遷移之主要因素，覆晶構裝必須具備良好的散熱能力，以降低錫鉛凸塊電子遷移之發生機率。本研究將針對散熱片材質及有機基板層數之不同，分析覆晶構裝之散熱能力以及介紹熱阻量測的方法，以提供較佳的散熱設計。最後將探討電流密度、環境溫度、針測壓痕、凸塊製程以及充填底膠，對共晶錫鉛凸塊電子遷移造成之影響，並提出電子遷移之設計準則。此外對於電流密度與晶片溫度之誤差，對電子遷移平均失效時間所造成之不確定性，也將一併予以探討。

Flip chip packaging has become popular due to its high density, short possible leads, fast signal transmission, low inductance, excellent noise control, good heat dissipation. Probe-after-bump has been the primary procedure for the flip chip device over the past decades, owing to the fact that it does not directly contact the bump pad, and possesses a better UBM (Under Bump Metallurgy) step coverage. However, the probe-after-bump procedure delays the yield feedback to the fab, and makes it hard to specify the responsibility for the low yield of the bumped wafer between the foundry fab and the bumping house. The probe-before-bump procedure can solve these problems, but probe marks may cause poor UBM step coverage, since a rugged pad surface causes problems for the UBM sputtering process. The probe tip may penetrate the pad metal due to excessive overdrive. Initially, this work develops an analytic methodology for the probe-before-bump procedure to predict the probing depth, and describes feasible probing design parameters to avoid over probing of the bump pad. It then presents a finite element method, and a probing experiment is performed to verify the analytical methodology results. The verified analytical methodology is employed to ascertain an adequate probing parameter for the probe-before-bump procedure. Next, this work determines the thin film mechanical properties of the wafer by nanoindentation, to derive the probing depth from the analytical methodology. In addition, chip temperature and current density are the main factors which impact the electromigration behavior. Lower thermal resistance implies better anti-electromigration capability. Moreover, this work investigates the heat dissipation capacity of flip chip packaging with an aluminum or copper heat spreader, and a four-layered or six-layered substrate. Furthermore, the probe mark and underfill impact on flip chip eutectic solder bump electromigration were investigated, and then the design rule of solder bump electromigration based on ten years (87,600 hours) life is presented. Finally, this study examines the uncertainty of MTTF (mean time to failure) which is caused by the tolerance of current density and chip operation temperature. Results of this study are used to develop an analytic methodology to predict the probing depth, and to acquire an adequate probing parameter which is accurate, cost effective and efficient. In addition, this work thoroughly elucidates the negligibly impacts of the probing mark on the solder bump electromigration.

[1] “SIA Roadmap”, 1997.
[2] J. M. Steigerwald, S. P. Murarga, and R. J. Gutmann, Chemical Mechanical Planarization of Microelectronic Materials, John Wiley & Sons, Inc., 1997.
[3] C. Chiang, P. S. Ho, T. M. Lu, J. T. Wetzel, “Low-Dielectric Constant Materials-Synthesis and Applications on Microelectronics”, Proceedings of MRS Symposium, Vol. 511, pp.3, 1988.
[4] M. B. Anand, M. Yamada, and H. Shibata, “Use of Gas as Low-K Interlayer Dielectric in LSI’s Demonstration of Feasibility”, IEEE Transaction Electron Devices, Vol. 44, pp. 1965-1971, Nov. 1997.
[5] S. Qin, et al, “Fabrication of Low Dielectric Constant Materials for ULSI Multilevel Interconnection by Plasma Ion Implantation”, IEEE Electron Device Letters, Vol. 19, pp. 420-422, Nov. 1998.
[6] T. Kikkawa, “Advanced Interconnect Technologies for ULSI Scaling”, IEEE 6th International Conference on VLSI and CAD, pp. 202-207, Seoul South Korea, Oct. 1999.
[7] M. Naik, et al, “Process Integration of Double Level Copper-Low k (k=2.8) Interconnect”, IEEE International Conference on Interconnect Technology, pp. 181-183, San Francisco, CA, US, May 1999.
[8] “IBM Makes Breakthrough To Copper”, Electronic Buyers News, Sep. 22, 1997.
[9] M. J. Varnau, “Impact of Wafer Probe Damage on Flip Chip Yields and Reliability”, IEEE/CPMT 19th International Electronics Manufacturing Technology Symposium, pp.293-297, Austin, TX, US, Oct. 1996.
[10] Q. Tan, C. Beddingfield, and A. Mistry, “Reliability Evaluation of Probe-before-Bump Technology”, IEEE/CPMT 24th International Electronics Manufacturing Technology Symposium, pp.320-324, Austin, TX, US, Oct. 1999.
[11] K. L. Johnson, Contact Mechanics, Cambridge University Press, 1985.
[12] J. B. Pethica, R. Hutchings, and W. C. Oliver, Philos. Mag. A 48, 593, 1983.
[13] W. C. Oliver, R. Hutchings, and J. B. Pethica, in ASTM STP 889, edited by P. J. Blau and B. R. Lawn (American Society for testing and Materials, Philadelphia, PA), pp. 90-108, 1986.
[14] M. F. Doerner and W. D. Nix, J. Mater. Res. 1, 601, 1986.
[15] W. C. Lover and G. M. Pharr, “An Improved Technique for Determining Hardness and Elastic Modulus using Load and Displacement Sensing Indentation Experiments”, J. Mater. Res., Vol. 7, No. 6, pp.1564-1583, June 1992.
[16] Y. P. Zheng and A. F. T. Mak, “An Ultrasound Indentation System for Biomechanical Properties Assessment of Soft Tissues in-vivo”, IEEE Transaction on Biomechanical Engineering, Vol. 43, No. 9, pp.912-918, 1996.
[17] Y. P. Zheng and A. F. T. Mak, “Extraction of Effective Young’s Modulus of Skin and Subcutaneous Tissues from Manual Indentation Data”, 1997 IEEE/EMBS, Proceedings –19th International Conference, pp. 2246-2249, Chicago, IL. USA, 1997.
[18] X. Wang, Y. Wang, G. Chen, and J. Liu, “Quantitative Estimate of the Characteristics of Conductive Particles in ACA by using Nano Indenter”, IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part A, Vol. 21, No. 2, pp. 248-251, June 1998.
[19] T. A. Venkatesh, K. J. Van Vliet, A. E. Giannakopoulos, and S. Suresh, “Determination of Elasto-Plastic Properties by Instrumented Sharp Indentation: Guidelines for Property Extraction”, Scripta Mater. 42, pp.833-839, 2000.
[20] J. C. Barbour, et al, “The Mechanical Properties of Aluminum Films Formed by Plasma Deposition and by Ion Irradiation of Sapphire”, Nuclear Instruments and Methods in Physics Research B, 166-167, pp. 140-147, 2000.
[21] R. Saha and W. D. Niz, “Effects of the Substrate on the Determination of Thin Film Mechanical Properties by Nanoindentation”, Acta Mater. 50, pp. 23-38, 2002.
[22] J. R. Black, “Mass Transport of an Aluminum by Momentum Exchange with Conducting Electrons”, IEEE/IRPS International Reliability Physics Symposium, 1967 6th Annual Proceeding, pp. 148-159, April 1967.
[23] I. A. Blech and E. S. Meieran, “Electromigration in Thin Aluminum Films”, Journal of Applied Physics, Vol. 40, pp.485-491, Feb. 1968.
[24] R. Rosenberg and M. Ohring, “Void Formation and Growth During Electromigration in Thin Film”, Journal of Applied Physics, Vol. 42, pp. 5671-5679, Dec. 1971.
[25] M. Shatzkes and J. R. Lloyd, “A Model for Conductor Failure Considering Diffusion Concurrently with Electromigration Resulting in a Current Exponent of 2”, Journal of Applied Physics, Vol. 59, pp. 3890-3893, June 1986.
[26] J. J. Clement and J. R. Lloyd “Numerical Investigations of the Electromigration Boundary Value Problem”, Journal of Applied Physics, Vol. 71, pp. 1729-1730, Feb. 1992.
[27] R. Kirchheim, “Stress and Electromigration in Al-lines of Integrated Circuits”, Acta Mater. Vol. 40, pp. 309-323, 1992.
[28] M. A. Korhonen, P. Borgesen, K. N. Tu, and C. Y. Li, “Stress Evolution Due to Electromigration in Confined Metal Lines”, Journal of Applied Physics, Vol. 73, pp. 3790-3799, Apr. 1993.
[29] A. S. Oates, “Current Density Dependence of Electromigration Failure of Submicron Width, Multilayer Aluminum Alloy Conductors”, Applied Physics Letter, Vol. 61, pp. 1475-1477, Apr. 1995.
[30] D. G. Pierce and P. G. Brusius, “Electromigration: A Review”, Microelectronics Reliability, Vol. 37, No. 7, pp. 1053-1072, 1997.
[31] C. K. Hu and J. M. E. Harper, “Copper Interconnections and Reliability”, Materials Chemistry and Physics, Vol. 52, pp. 5-16, 1998.
[32] J. J. Clement, “Electromigration Modeling for Integrated Circuit Interconnect Reliability Analysis”, IEEE Transaction on Device and Materials Reliability, Vol. 1, No. 1, pp. 33-41, March 2001.
[33] “Assembly and Packaging”, International Technology Roadmap for Semiconductors, p.223, 1999 Edition.
[34] Brandenburg, Scott, et al, “Electromigration Studies of Flip Chip Solder Joints”, Proceeding Surface Mount International, San Jose, CA, Sep. 1998.
[35] C. Y. Liu, C. Chen, C. N. Liao, and K. N. Tu, “Microstructure- Electromigration Correlation in a Thin Strip of Eutectic SnPb Solder Stressed Between Cu Electrodes”, Applied Physics Letters, Vol. 75, No. 1, pp.58-60, July 1999.
[36] C. Y. Liu, C. Chen, and K. N. Tu, “Electromigration in Sn-Pb Solder Strips as a Function of Alloy Composition”, Journal of Applied Physics, Vol. 88, No. 10, pp.5703-5709, Nov. 2000.
[37] P. Elenius, H. Yang, and R. Benson, “Solder Bars-A Novel Flip Chip Application for High Power Devices”, IEEE Electronic Components and Technology Conference, pp. 697-701, Las Vegas, NV, US, May 2000.
[38] T. Y. Lee, K. N. Tu, S. M. Kuo, and D. R. Frear,”Electromigration of Eutectic SnPb Solder Interconnects for Flip Chip Technology”, Vol. 89, No. 6, pp. 3189-3194, Mar. 2001.
[39] Q. T. Huynh, et al, “Electromigration in Eutectic SnPb Solder Lines”, Journal of Applied Physics, Vol. 89, No. 8, pp. 4332-4335, Apr. 2001.
[40] T. Y. Lee, K. N. Tu, and D. R. Frear,” Electromigration of Eutectic SnPb and SnAg3.8Cu0.7 Flip Chip Solder Bumps and Under-Bump Metallization”, Journal of Applied Physics, Vol. 90, No. 9, pp. 4502-4508, Nov. 2001.
[41] K. Nakagawa, et al, “Thermo-Electromigration Phenomenon of Solder Bump, Leading to Flip-Chip Devices with 5,000 Bumps”, Electronic Components and Technology Conference, pp. 971-977, Orlando, FL, US, June 2001.
[42] T. Y. Tom Lee, T. Y. Lee, and K. N. Tu, “A Study of Electromigration in 3D Flip Chip Solder Joint Using Numerical Simulation of Heat Flux and Current Density”, Electronic Components and Technology Conference, pp. 558-563, Orlando, FL, US, June 2001.
[43] C. C. Yeh, W. J. Choi, and K. N. Tu, “Current-Crowding-Induced Electromigration Failure in Flip Chip Solder Joints”, Journal of Applied Physics, Vol. 80, No. 4, pp. 580-582, Jan. 2002.
[44] W. J. Choi, E. C. C. Yeh, and K. N. Tu, “Electromigration of Flip Chip Solder Bump on Cu/Ni (V)/Al Thin Film Under Bump Metallization”, IEEE Electronic Components and Technology Conference, pp. 1201-1205, San Diego, CA, US, May 2002.
[45] N. Sporck, “A New Probe Card Technology Using Compliant Microsprings”, Proceedings of the International Test Conference, pp. 527-532, Washington, DC, USA, Nov. 1997.
[46] C. Barsotti, S. Tremaine, and M. Bonham, “Very High Density Probing”, Proceeding of the 1988 International Test Conference, pp. 608-614, Washington, DC, US, Sep. 1988.
[47] N. Nadeau and S. Perreault, “An Analysis of Tungsten Probes’ Effect on Yield in a Production Wafer Probe Environment”, Proceedings of the International Test Conference, pp. 208-215, Washington, DC, US, Aug. 1989.
[48] B. Leslie, F. Matta, “Wafer-Level Testing with a Membrane Probe”, IEEE Designs & Test of Computers, pp. 10-17, Feb. 1989.
[49] J. A. Gasbaarro and M. A. Horowitz, “Integrated Pin Electronics for VLSI Functional Testers”, IEEE Journal of Solid State Circuits, Vol. 24, pp. 331-337, Apr. 1989.
[50] B. Leslie and F. Matta, “Membrane Probe Card Technology”, IEEE Proceedings International Test Conference, pp. 601-607, 1989.
[51] M. Beiley, F. Ichishita, C. Nguyen, and S. Wong, “Array Probe Card”, Proceedings of the 1992 IEEE Multi-Chip Module Conference, pp. 28-31, Santa Cruz, CA, US, Mar. 1992.
[52] J. Kister and R. L. Franch, “Advances in Membrane Probe Technology”, Proceedings of the 1992 International Test Conference, pp. 927-935, Sep. 1992.
[53] S. Kasukabe, S. Harada, T. Maruyama, and R. Takagi, “Contact Properties of the Spring Probe for Probing on a Solder Bump”, Proceedings of the 38th IEEE Holm Conference on Electrical Contacts, pp. 187-190, Philadelphia, PA, US, Oct. 1992.
[54] Y. Kondoh and T. Ueno, “Universal Membrane Probe for Known Good Die”, Proceedings of the 1994 International Conference on Multichip Modules, pp. 248-254, Apr. 1994.
[55] M. Beiley, J. Leung, and S. S. Wong, “A Micromachined Array Probe Card—Fabrication Process”, IEEE Transaction of Components, Packaging, Manufacturing Technology, part B, Vol. 18, pp. 179-183, Feb. 1995.
[56] Y. Zhang, D. Worsham, D. Morrow, and R. B. Marcus, “ A new MEMS Wafer Probe Card”, Proceedings of the 10th IEEE International Workshop on MEM’s, pp. 395-399, Nagoya, Japan, Jan. 1997.
[57] N. Sporck, “A New Probe Card Technology Using Compliant Microsprings”, Proceedings of the 1997 International Test Conference, pp. 527-532, Washington, DC, US, Nov. 1997.
[58] F. L. Taber, “An Introduction to Area Array Probing”, IEEE International Test Conference, pp. 277-281, Washington, DC, US, Oct. 1998.
[59] T. Ito, R. Sawada, and E. Higurashi, “Micro IC Probe for LSI Testing”, 12th IEEE International Conference on Micro Electro Mechanical Systems, pp. 263-266, Orlando, FL, US, Jan. 1999.
[60] Y. Zhang, Y. Zhang, and R. B. Marcus, “Thermally Actuated Microprobes for a New Wafer Probe Card”, IEEE Journal of Microelectromechanical Systems, Vol. 8, No. 1, pp. 43-49, March 1999.
[61] M. Zargari, et al, “A BiCMOS Active Substrate Probe-Card Technology for Digital Testing”, IEEE Journal of Solid-state Circuits, Vol. 34, No. 8, pp. 1118-1135, August 1999.
[62] S. Maekawa, et al, “ Highly Reliable Probe Card for Wafer Testing”, Proceedings of the 50th IEEE Electronic Components and Technology Conference, pp. 1152-1156, Las Vegas, NV, US, May 2000.
[63] B. H. Kim, et al, “A Novel MEMS Silicon Probe Card”, The 15th IEEE International Conference on Micro Electro Mechanical Systems, pp. 368-371, Jan. 2002.
[64] www.Formfactor.com, Southwest Workshop, June 1999.
[65] D. Genin and M. Wurster, ”Probing Consideration in C-4 Testing of IC Wafers”, Int’l Journal of Microcircuits and Electronic Packaging, Volume 12, Number 4, Forth Quarter 1992 (ISSN 1063-1674).
[66] Cobra Probe, Probe cards information.” www.kns.com”, 2001.
[67] J. H. Lau, Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, McGraw-Hill, 2000.
[68] L. Li, P. Thompson, “Stencil Printing Process Development for Flip Chip Interconnect”, IEEE Transaction on Electronics Packaging Manufacturing, Vol. 23, No. 3, pp. 165-170, July 2000.
[69] Y. Kumano, “Development of Chip-on-Flex Using SBB Flip-Chip Technology”, Microelectronics Reliability, Vol. 41, pp.525-530, 2001.
[70] J. K. Lin, T. Fang, and R. Bajaj, ”Squeegee Bump Technology”, IEEE Transaction Components and Packaging Technologies, Vol. 25, No. 1, pp. 38-44, March 2002.
[71] Prismark Presentation in Advanced Package Developments, Nanomaterials, and Embedded Passives Conference, pp. 16-17, HsinChu, Taiwan, May 9, 2002.
[72] A. E. H. Love, A Treatise on the Mathematical Theory of Elasticity, Dover, 1944.
[73] “Guideline for Measurement of Electronic Package Inductance and Capacitance Model Parameters,” EIA/JEP 123, October 1995.
[74] W. S. Janna, Engineering Heat Transfer, PWS Engineering, 1986.
[75] W. C. Oliver and G. M. Pharr, “An Improved Technique for Determining Hardness and Elastic Modulus Using Load and Displacement Sensing Indentation Experiments”, Journal of Materials Research, Vol. 7, No. 6, pp. 1564-1583, June 1992.
[76] M. S. Guzman, M. Hack, and G. Neubauer, “ Mechanical Properties and Adhesion Measurements on Films used in Advanced Packages”, 1994 IEEE International Reliability Physics Symposium, pp. 108-113, San Jose, CA.
[77] T. Sugimoto and T. Kawaguchi, “ Development of an Automatic Vickers Hardness Testing System Using Image Processing Technology”, IEEE Transaction on Industrial Electronics, Vol. 44, No. 5, pp. 696-702, October, 1997.
[78] Y. Tsukamoto, H. Yamaguchi, and M. Yanagisawa, “Mechanical Properties of Thin Films: Measurements of Ultramicroindentation Hardness, Young’s Modulus and Internal Stress”, Thin Solid Films, 154, pp.171-181, 1987.
[79] R. A. Andrievskiî, et al, “Nanoindentation and Strain Characteristics of Nanostructured Boride/Nitride Films”, Physics of the Solid State, Vol. 42, No. 9, pp. 1671-1674, 2000.
[80] T. A. Venkatesh, K. J. Van Vliet, A. E. Giannakopoulos, and S. Suresh, “Determination of Elasto-Plastic Properties by Instrumented Sharp Indentation: Guideline for Property Extraction”, Scripta Materials, Vol. 42, No. 9, pp.833-839, 2000.
[81] X. Li and B. Bhushan, “ Dynamic Mechanical Characterization of Magnetic Tape Using Nanoindentation Techniques”, IEEE Transactions on Magnetics, Vol. 37, No. 4, pp. 1616-1619, July 2001.
[82] M. O’Hern, “Developments in Diamond Indentation and Scratch Tips: Introducing the AccuTip Family of Diamond Tips”, www.mts.com/nano/XP_specs, 2002.
[83] C. Xie, “Nano Indenter XP Testing System”, MTS Systems Corporation Introduction Materials, Nov. 2002.
[84] MTS Manual, “TestWorks 4 Software for Nanoindentation Systems”, Version: 012, Document No.: D1418XPA-10629, 1999.
[85] “Test Method for Still-Air and Force-Air Junction-To-Ambient Thermal Resistance Measurements of Integrated Circuit Packages”, SEMI G38-0996, 1996.
[86] C. Y. Chang, S. M. Sze, ULSI Technology, McGraw-Hill, 1996.
[87] J. H. Lau, Y. H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, 1997.
[88] C. Lipson, N. J. Sheth, Statistical Design and Analysis of Engineering Experiments, McGraw-Hill, 1973.
[89] H. C. Cheng, K. N. Cheng, and C. K. Chen, “Parametric Analysis of Thermally Enhanced BGA Reliability Using a Finite-Volume- Weighted Averaging Technique”, 1998 International Mechanical Engineering Congress and Exposition, EEP-Vol.24, pp. 13-20, November, Anaheim, CA, 1998.
[90] Y. T. Lin, K. C. Chang, C. T. Peng, and K. N. Chiang, "Parametric Design and Reliability Analysis of WIT Wafer Level Packaging", ASME Transaction, Journal of Electronic Packaging, Vol. 124, No.3, pp.234-239, Sept. 2002.
[91] K. N. Chiang, C. N. Liu, and C. T. Peng, "Parametric Reliability Analysis of No-Underfill Flip Chip Package", IEEE Transactions on Components and Packaging Technologies, Vol.24, No.4, pp.635-640, Dec. 2001.
[92] J. P. Holman, Experimental Methods for Engineers, McGraw-Hill, 1994.
[93] P. Lall, M. G. Pecht, E. B. Hakim, Influence of Temperature on Microelectronics and System Reliability, CRC Press, 1997.