在這篇論文之中，我們將介紹一個新的階層式可程式規劃邏輯陣列硬體架構，這個硬體架構適用於單晶片系統核心，因為用新的架構不會侵犯傳統的可程式規劃邏輯陣列的智慧財產權，也可以有較好的電路效能，以及可預測的電路延遲時間，由於要用在單晶片系統之中，這個新的可程式規劃邏輯陣列架構並不是為了普遍的功能而是為了特殊的功能而設計，所以不需要使用傳統的架構，由於有了這個新的階層式可程式規劃邏輯陣列硬體架構，還需要有能配合它的設計編譯器，才能將設計實現出來，這個為了新的階層式可程式規劃邏輯陣列硬體架構而設計編譯器中包含了三個部分，第一部分是技術映成，第二部分是叢集，第三部分是放置和繞線，因此我們也會研究階層式可程式規劃邏輯陣列以速度為取向的叢集的問題。我們會展示一個有效率的三階層啟發式的叢集演算法。延遲時間多寡和面積大小的取捨可以利用節點複製來進行控制，如果要有最短的延遲時間，所需要的面積可能會比稍微長一點的延遲時間需要的面積多好幾倍，因此，此篇論文的目的在給定每一層的節點數和每一層的連線數和延遲時間的限制下，達到最小的使用面積，而要複製的節點都是有多扇出的節點。實驗結果顯示我們所提出的演算法和以面積為取向的演算法[11]比較可以改進電路的效能達到百分之十。

In this thesis, we study the problem of performance-driven multi-level circuit
clustering with application to hierarchical FPGA designs.

We present an efficient three-level clustering

heuristic algorithm for delay minimization.

The trade-off of area and delay can be controlled

by node duplications.

Experiment results show that our algorithm can improve the

circuit performance by 10% as compared

to an area-driven clustering tool [11].

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