近年來，晶片運作時所消耗的功率漸漸受到設計者的重，尤其是近年來廣泛研究的低功率晶片設計。功率消耗一般來說可以分為瞬間最大功率以及平均功率。過大的瞬間功率會造成整個電路效能以及可靠性的問題。電腦輔助設計(CAD)必須幫助設計者在設計時快速而且準確的估計正確的功率，讓設計者可以及早更改設計。
為了找出電路最大的瞬間最大功率，往往要把整個電路的功能性輸入訊號全部都模擬過才可以確定。所以瞬間最大功率的問題，第一個是速度。另外一個估測瞬間最大功率的問題則是準確性。使用電晶體階層的模擬方法才能準確的估測電路的瞬間最大功率消耗，但這種方法往往花費過多的時間而顯的沒有效率。
為了同時解決估測瞬間最大功率在速度上以及準確性的問題，我們提出了混合階層的估測方法。主要分成兩個階段：（1）延遲時間模型的建立，以及（2）波形回復的階段。在第一個階段，我們由邏輯層次以及電晶體層次模擬的結果找出兩者的關係，建立一個新的模型。在第二階段，利用建立好的模型，將功能性訊號的在邏輯層次模擬的結果回復成近似電晶體層次的模擬結果。
實驗結果顯示，此種方法可以有效的保存電晶體層次的訊息，同時可以利用邏輯層次快速模擬的優點。在速度方面，僅比邏輯階層模擬時間多一點，在準確度上，可以到達90%以上的電晶體階層模擬的準確度。

In this thesis, we present a mixed-level methodology for estimating the peak power dissipation of a logic IC. The ultimate goal is to mix the speed of a logic simulator with the accuracy of a transistor-level simulator. There are two major techniques in this methodology. Firstly, we attempt to establish the delay correlations of two simulators at different level of abstractions through a technique called delay calibration. Secondly, we use simple waveform shaping to re-generate the accurate waveforms of signals based on the calibrated delay information. By doing so, the time-consuming simulation at the transistor level can be skipped without losing much accuracy. Experimental results on a number practical design block shows that it is 30% more accurate than a pure gate-level simulator on the average.

[1] N. Najm,“A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol.2, NO.4, December 1994.
[2] J. Lu and Z. Lin, “Effects of Delay Models on Maximum Power Estimation of VLSI Circuits,” ASIC Proc. 4th Int’l Conf., pp. 179-182, October 2001.
[3] M. S. Hsiao, E. M. Rudnick, and J.H. Patel, “Effects of Delay Models on Peak Power Estimation of VLSI Sequential Circuits,” Proc. of Int’l Conf. on Computer-Aided Design, pp. 45-51, 1997.
[4] H. Kriplani, F. N. Najm, and I. N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,” IEEE Trans. on Computer-Aided Design, pp. 998-1012, Aug. 1995.
[5] Y. M. Jiang, A. Krstic, and K. T. Cheng, “Estimation for Maximum Current Through Supply Lines for CMOS Circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol.8, NO.1, February 2000.
[6] Y. M. Jiang, K. T. Cheng, and A. Krstic, ” Estimation Of Maximum Power And Instantaneous Current Using A Genetic Algorithm,” Proc. Of Custom Integrated Circuits Conf., pp. 135 – 138, 1997.
[7] M S. Hsiao, “Peak Power Estimation Using Genetic Spot Optimization For Large VLSI Circuits,” Proc. of Int’l Conf. on Design Automation and Test In Europe, pp. 175-179, 1999.
[8] A. Krstic and K.T. Cheng, “Vector Generation for Maximum Instantaneous Current Through Supply Lines For CMOS Circuits,” Proc. of Design Automation Conf., pp. 383-388, 1997.
[9] C. Y. Wang, K. Roy, and T. L. Chou, “Maximum Power Estimation For Sequential Circuits Using A Test Generation Based Technique,” Proc. of IEEE Custom Integrated Circuits Conf., pp. 229-232, 1996.
[10] C. Y. Wang and K. Roy, “COSMOS: A Continuous Optimization Approach For Maximum Power Estimation Of CMOS Circuits,” Proc. of Int’l Conf. on Computer-Aided Design, pp. 52-57, 1997.
[11] Y. M. Jiang and K. T. Cheng, “Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits,” Proc. of Int’l Conf. on Design Automation and Test in Europe., pp. 698-702, 1998.