在深次微米積體電路技術中,連線延遲成為了影響IC晶片效能的主要因素。在擺放與繞線階段，線長的減少為最主要的目標。比較傳統的曼哈頓架構，新架構－X與Y架構－，在不同的金屬線層提供更多元的繞線方向來接線，以減少線長。然而，為支援多方向的繞線，多金屬線層的交錯，造成更多非預期的鑽孔數目。
在本論文中，我們提出一個在λ平面兩階段的時鐘繞線演算法。概略繞線階段，針對λ平面提出一個普遍的零時序且最小線長的時鐘樹建立演算法。細部繞線階段，用兩個有效果且有效率的方式(NVM與BVM)減少潛在鑽孔數。比較曼哈頓架構，λ幾何時鐘樹繞線器，在Y架構有平均7.57% 與X架構平均9.68% 線長的減少。數據中顯示NVM與BVM方法應用在Y架構17%與X架構37%平均的鑽孔減少。

In deep sub-micron VLSI technologies, the interconnect delay has become a dominant factor affecting performance of ICs. Wirelength reduction is the most fundamental objective in the P&R stage. Compared with traditional Manhattan architecture, X-architecture and Y-architecture—the new architectures—, provide more available routing directions correspond to different metal layers for chip interconnection to reduce wire length. However, these cause a lot of unexpected via count as a result of multiple metal layers being crossed in order to achieve specialized routing direction.
In this paper, we propose a two-stage clock routing algorithm for λ-geometry plane. In global routing stage, we present a general zero skew clock tree construction algorithm with minimum wirelength under any kinds of routing architecture (λ-ZST). In detailed routing stage, two effective and efficient approaches (NVM and BVM) are used for decreasing the potential via count. Compared with the Manhattan architecture, our λ-geometry clock router achieves, on average, a 7.57% wirelength reduction in Y-architecture and 9.68% in X-architecture. In our experimental result, using NVM and BVM shows an average reduction in the via count of 17% in Y-architecture and 37% in X architecture respectively.

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