隨著製程演進，單晶片網路上結點間的連結線數量也隨之增長，所需要的暫存器數量也同步成長。而單晶片網路上之功耗越來越值得重視，其中暫存器所產生的功耗佔了相當的比例。本論文提出了一個結合電路交換與封包交換的混合型單晶片網路設計，此網路中所需的暫存器數量可大幅減少，且不會隨連結線數量上升而增加。在效能方面，此網路使用了簡單的保留反向路徑方式來建構電路交換網路的路徑，以隱藏建立路徑所需的延遲。
模擬結果顯示，所提出之混合型網路，與傳統封包交換網路相較，在連結線數量為128位元時，所需之功耗為傳統封包交換網路的56%，面積為52%，且有1.1%的效能增益。當連結線數量增加至256位元時，相對於傳統封包交換網路，所需之功耗為32%，面積為40%，且有1.4%的效能增益。

As the CMOS technology develops, the number of buffers required in a network-on-chip increases with flit width. This increase of buffers provides more power and area overhead to a network router. This thesis proposes a hybrid packet-switched and circuit-switched network in which the total buffer requirement depends on only the width of the short message and buffer depth, and does not increase with the network width. The performance is maintained through a low latency circuit-switch by using a simple reverse path reservation method.
The simulation results indicated that, the proposed network costs 56% of power consumption and 52% of area overhead, accompanied by 1.1% of performance improvement compared with the baseline network under the 128-bit network width configuration. And the power consumption and area overhead of proposed network reduce to 32% and 40%, respectively, while exhibiting 1.4% performance improvement compared with the baseline network under the 256-bit network width con-figuration.

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