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研究生： 楊惠婷
Hui-Ting Yang
論文名稱： 一個以字典為基礎的高效率顯示畫面壓縮器
An Efficient Dictionary-based Display Frame Compressor
指導教授： 林永隆
Youn-Long Lin
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 42
中文關鍵詞： 以字典為基礎 、壓縮器
外文關鍵詞： Dictionary-based, Compressor
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    • H.264/AVC 是一個新興的視頻壓縮編碼標準，其在相同的影像品質下能比先前的編碼標準減少大約50%之碼率。然而，當視頻壓縮應用之畫面解析度越高時，在有限時間內所需處理的資料量也越大。基於成本的考量，這些資料通常儲存於外部存取速度較慢的動態隨機存取記憶體(DRAM)，因此導致大量的記憶體頻寬需求與系統瓶頸。本論文為顯示畫面提出一個有效的以字典為基礎之壓縮與解壓縮演算法，並且應用於H.264解碼器上。模擬結果顯示，本論文所提出的演算法在1080HD畫面解析度之下平均可以達到54%的壓縮率，而總記憶體存取流量平均減少了34%。因此，匯流排只需要運作在57MHz的時脈下，即可即時(real-time)解壓縮1080HD的畫面解析度。

    H.264/AVC is an emerging video coding standard that provides about 50% bit rate reduction relative to the performance of prior standards at the same quality level. However, as the resolution of video coding applications becomes high, a large amount of data is required for processing within a bounded time. For cost reason, they are usually stored in slow external DRAM, and thus resulting in high memory bandwidth requirements and system bottleneck. This thesis proposes an efficient dictionary-based compression and de-compression algorithm for display frames and presents its implementation in an H.264 decoder. Simulation result shows that the proposed algorithm achieves 54% of compression ratio in 1080HD resolution and 34% of total memory traffic reduction on average. Hence, the bus only has to run at 57 MHz to support 1080HD real-time decoding.

    Abstract I Contents II List of Figures III List of Tables IV Chapter 1 Introduction 1 1.1 Overview 1 1.2 NTHU H.264/AVC Decoder System 2 Chapter 2 Related Works 7 2.1 Memory Traffic Reduction Techniques 7 2.2 Previous Works 9 Chapter 3 Analysis of Pixel Distribution 13 3.1 Spatial Locality of Frame Pixels 13 3.2 Correlation of Adjacent Pixels 16 Chapter 4 Proposed Architecture 20 4.1 Overview of the Proposed Architecture 20 4.2 Display Frame Compressor 21 4.2.1 Architecture of Display Frame Compressor 21 4.2.2 Proposed Compression Algorithm 22 4.2.3 Hardware Implementation 24 4.2.3.1 Codeword Size Selection 24 4.2.3.2 Architecture of Display Frame Compressor Core 25 4.2.3.3 Memory Organization 26 4.3 Display Frame De-compressor 29 4.3.1 Architecture of Display Frame De-compressor 29 4.3.2 Proposed De-compression Algorithm 30 4.3.3 Hardware Implementation 31 4.3.3.1 Architecture of Display Frame De-compressor Core 31 4.3.3.2 Memory Organization 33 Chapter 5 Experimental Results 34 5.1 Synthesis Result 34 5.2 Simulation Result 35 5.2.1 Data Reduction Ratio 35 5.2.2 Memory Traffic Reduction 37 Chapter 6 Conclusion 39 Bibliography 40

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