傳統上，邏輯電路設計合成和佈局繞線是分開來執行。隨著晶片設計產業進入深次微米時代，繞線上的時序延遲已經遠大於邏輯電路細胞本身的時序延遲，因此想要依照舊有的特殊應用晶片設計流程，用不考慮真正佈局繞線的時序資訊而以邏輯電路細胞為時序主要考量的方法來預測當繞線完成時最後的電路的真正時序，在這種情況下想完成無時序延遲的晶片設計已是不可能達成的任務。因此在這種情況下如果能將邏輯電路設計合成和佈局繞線整合起來是一種可行的辦法。
依據這種想法，在這篇論文中，我們提出了一種改進目前深次微米特殊積體電路設計流程的方法，這個方法將整個晶片設計的流程從硬體硬體描速語言為基礎架構到最後的佈局繞線整個地整合起來，在其中我們加入了若干的步驟包括了邏輯電路設計階層資訊的保存、軟模組的粹取、佈局和合成等。讓晶片邏輯設計時的架構資訊能加以保存並在軟模組的粹取和佈局上運用這些資訊，並且將真正佈局繞線完成的資訊也加以粹取，讓我們於修正時能有更接近真實的資訊可以運用，使得整個電路設計能於最少的反覆修正中就達到規格所要求的時序。

我們將這所提出的方法運用在一些工業界真實的晶片設計上，同時採用傳統的工業界設計流程為一對照組加以比較，實驗結果證實我們所提出的方法的確能有效地縮短晶片設計的最差路徑時序延遲。

---

Previously, logic synthesis and physical design have been performed
separately.

During logic synthesis, only gate delays are available when

estimating interconnection delays.

The synthesis result is only as good as the estimation

accuracy.

As the IC industry moves towards deep sub-micron era,

interconnection delay will overwhelm gate delays.

Accurately estimating without a link to the layout synthesis

is impossible since the interconnection delays

heavily depend on the layout.

Therefore, a feasible solution would be to integrate logic

and physical design.

In this thesis, we address several timing-driven approaches and

present an integrated chip implementation flow that

incorporates a floorplanning-guided soft-macro placement and re-synthesis

method for area and timing improvement.

In the timing closure design flow, the major deep sub-micron

layout electrical characteristics are also considered.

First, we present a performance-driven soft-macro clustering and placement

method

that utilizes the Hardware Description Language(HDL) design hierarchy.

Second, a timing closure flow is developed to exploit the interaction between

logic synthesis and physical design.

During each iteration, soft-macros are re-synthesized with either a

relaxing or a tightening timing constraint based on

the post-layout timing information from the previous iteration.

Doing so allows us to produce area-efficient designs while satisfying the timing

constraints.

Experiments on several industrial designs ranging from 75K to 230K

gates demonstrate that the proposed

method reduces critical-path delay by an average of 22\%.

\bibitem{Abouzeid}
P. Abouzeid, K. Sakouti, G. Saucier and F. Poirot,
``Multi-level synthesis minimizing the routing factor,''
{\em Proc. of the 27th Design Automation Conference},
pp. 365-368, 1990.
\bibitem{alpe95}
C. J. Alpert and A. B. Kahng,
``Recent Direction in Netlist Partitioning: A Survey,''
{\em INTEGRATION: the VLSI Journal}, N19,
pp. 1-81, 1995.
\bibitem{Alpert99}
C. J. Alpert, A. Devgan and S. T. Quay
``Buffer Insertion With Accurate Gate and Interconnect Delay
Computation,''
{\em Proc. of the 36th Design Automation Conference},
pp. 479-484, 1999.
\bibitem{Alpert991}
C. J. Alpert, A. Devgan and S. T. Quay
``Buffer Insertion for Noise and Delay Optimization,''
{\em IEEE Trans. on Computer-Aided Design,} vol. 18,
pp. 1633-1645, November, 1999.
\bibitem{Aoki95}
T. Aoki, M. Murakata, T. Mitsuhashi and N. Goto,
``Fanout-tree restructuring algorithm for post-placement
timing optimization,''
{\em Proc. of Asia and South Pacific Design Automation Conf.},
pp. 417-422, 1995
\bibitem{baza98}
K. Bazargan, S. Kim and M. Sarrafzadeh,
``Nostradamus: A Floorplanner of Uncertain Design,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 18-23, 1998.
\bibitem{Boese93}
K. D. Boese, A. B. Kahng and G. Robins,
``High-Performance Routing Trees With Identified Critical Sinks,''
{\em Proc. of the 30th Design Automation Conference},
pp. 182-187, 1993.
\bibitem{Boe95}
K. D. Boese, A. B. Kahng, B. A. McCoy, and G. Robins,
``Near-Optimal Critical Sink Routing Tree Constructions,''
{\em IEEE Trans. on Computer-Aided Design,} vol. 14, no. 12
pp. 1417-1436, December 1995.
\bibitem{Brasen90}
D. R. Brasen and M. L. Bushnell,
``MHERTZ: a new optimization algorithm for floorplanning and
blobal routing,''
{\em Proc. of the 27th Design Automation Conference},
pp. 107-110, 1990.
\bibitem{bush97}
R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher,
S. Grout, G. Ledenbach, Nagaraj NS and R. Steele,
``Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven
Physical Design into the 21th Century,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 212-217, 1997.
\bibitem{Chang94}
Chwen Cher Chang, J. Lee,
M. Stabenfeldt, R.-S. Tsay,
``A practical all-path timing-driven place and route design system,''
{\em Proc. of IEEE Asia-Pacific Conference on Circuits and Systems},
pp. 560-563, 1994.
\bibitem{Cheng84}
C.-K. Cheng and E. S. Kuh,
``Module placement based on resistive network optimization,''
{\em IEEE Trans. on Computer-Aided Design}, vol. CAD-3,
pp. 218-225, July 1984.
\bibitem{comp97}
R. Composano,
``The Quarter Micron Challenge: Integrating Physical and Logic Design,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 211, 1997.
\bibitem{Cong93}
J. Cong, K. S. Leung and D. Zhou,
``Performance-driven interconnect design based on
distributed RC delay model,''
{\em Proc. of the 30th Design Automation Conference},
pp. 606-611, 1993.
\bibitem{Con95}
J. Cong and D. Xu,
``Exploiting signal flow and logic dependency in standard cell placement,''
{\em Proc. of Asia and South Pacific Design Automation Conf.},
pp. 399-404, 1995.
\bibitem{Cong95k}
J. Cong and K. S. Leung,
``Optimal Wiresizing Under Elmore Delay Model,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 14, no. 3,
pp. 321-336, 1995.
\bibitem{Deguchi98}
T. Deguchi, T. Koide and S. Wakabayashi,
``A performance-driven global routing algorithm with wire-sizing
and buffer-insertion,''
{\em Proc. of IEEE Asia-Pacific Conference on Circuits and Systems},
pp. 121-124, 1998.
\bibitem{Dey91}
S. Dey, F. Beglez and G. Kedem,
``Circuit partitioning for logic synthesis,''
{\em IEEE Journal of Solid-Stage Circuits}, vol. 26,
pp. 350-363, March 1991.
\bibitem{Dunlop84}
A. E. Dunlop, V. D. Agrawal,
D. N. Deutsch, M. F. Jukl, P. Kozak and M. Wiesel,
``Chip layout optimization using critical path
weighting,''
{\em ACM/IEEE DAC}, vol. 21,
pp. 133-136, 1984.
\bibitem{Dunlop85}
A. Dunlop and B. Kernighan,
``A procedure for placement for very large circuits,''
{\em IEEE Trans. on Computer Aided Design}, vol. CAD-4,
pp. 92-98, January 1985.
\bibitem{Eise98}
Hans Eisenmann and Frank M. Johannes,
``Generic Global Placement and Floorplanning,''
{\em Proc. of the 35th Design Automation Conference},
pp. 269-274, 1998.
\bibitem{Elmore}
W.~C.~Elmore,
``The transient response of dampen linear
networks with particular regard to wide
band amplifiers,''
{\em J.~Appl. Phys.}, vol.19, pp. 55-63, 1948.
\bibitem{fm}
C. M. Fiduccia and R. M. Mattheyses,
``A Linear Time Heuristic for Improving Network Partitions,''
{\em Proc. of the 19th Design Automation Conference},
pp. 175-181, 1982.
\bibitem{Gosti98}
Wilsin Gosti, Amit Narayan, Robert K. Brayton and
Alberto L. Sangiovanni-Vincentelli,
``Wireplanning in Logic Synthesis,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 26-33, 1998.
\bibitem{Hodes94}
T. D. Hodes, B. A. McCoy, G. Robins,
``Dynamically-Wiresized Elmore-Based Routing Constructions,''
{\em Proc. of IEEE Int. Symp. on Circuits and Systems},
1994.
\bibitem{Holt97}
G. Holt and A. Tyagi,
``Minimizing Interconnect Energy Through Integrated Low-Power
Placement and Combinational Logic Synthesis,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 48-53, 1997.
\bibitem{hou98}
H. Hou and S. Sapatnekar,
``Routing Tree Topology Construction to Meet Interconnect
Timing Constraints,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 205-209, 1998.
\bibitem{Huang97}
D. J.-H Huang and A. B. Kahng,
``Partitioning based standard cell global placement
with an exact objective,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 18-25, 1997.
\bibitem{Jackson87}
M. A. B. Jackson, E. S. Kuh and M. Marek-Sadowska
``Timing-Driven Routing for Building Block Layout,''
{\em Proc. of IEEE Intl. Symp. on Circuits and Systems},
pp. 518-519, 1987.
\bibitem{Jackson89}
M. A. B. Jackson and E. S. Kuh,
``Performance-driven placement for cell based IC's,''
{\em ACM/IEEE DAC}, vol. 26,
pp. 370-375, 1989.
\bibitem{Kang97}
M. Kang, W.W.-M. Dai, T. Dillinger
and D. Lapotin,
``Delay bounded buffered tree construction for timing
driven floorplanning,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 707-712, 1997.
\bibitem{Kleinhans91}
J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich,
``GORDIAN: VLSI placement by quadratic programming
and slicing optimization,''
{\em IEEE Trans. on Computer-Aided Design}, vol. CAD-10,
pp. 356-365, Mar 1991.
\bibitem{Knapp92}
D. W. Knapp,
``Fasolt: A Program for Feedback-Driven Datapath Optimization,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 11,
pp. 677-695, 1992.
\bibitem{Koehl98}
J. Koehl, U. Baur, T. Ludwig, B. Kick and T. Pflueger,
``A flat, timing-driven design system for a
high-performance CMOS processor chipset,''
{\em Proc. of Design, Automation and Test in Europe},
pp. 312-320, 1998.
\bibitem{Koide98}
T. Koide and S. Wakabayashi,
``A timing-driven global routing algorithm with pin assignment,
block reshaping, and positioning for building block layout,''
{\em Proc. of Asia and South Pacific Design Automation Conference},
pp. 577-583, 1998.
\bibitem{kuet97}
K. Keutzer, A. R. Newton, and N. Shenoy,
``The future of Logic Synthesis and Physical Design in Deep-Sub-micron
Process Geometries,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 218-223, 1997.
\bibitem{kuh97}
E. S. Kuh,
``Physical Design: Reminiscing and Looking Ahead,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 206, 1997.
\bibitem{Kurdahi93}
F. Kurdahi, D. D. Gajski, C.Ramachandran
and V. Chaiyakul,
``Linking Register-Transfer and Physical Levels of Design,''
{\em Trans. on Information and Systems},
September 1993.
\bibitem{Lalgudi95}
Kumar N. Lalgudi and Marios C. Papaefthymiou,
``DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling,''
{\em 32nd ACM/IEEE Design Automation Conference},
pp. 304-309, June, 1995.
\bibitem{Leiserson}
C. E. Leiserson and J. B. Saxe,
``Retiming Synchronous Circuitry,''
{\em Algorithmica}, vol. 6,
pp. 5-35, 1991.
\bibitem{leng90}
T. Lengauer,
{\em Combinatorial Algorithms for
Integrated Circuit Layout}, Wiley, 1990.
\bibitem{Lillis95}
J. Lillis, C. K. Cheng and T. T. Lin,
``Optimal Wire Sizing for Low Power and a Generalized
Delay Model,''
{\em Proc. of Int. Conf. Computer-Aided Design},
1995.
\bibitem{Lionel97}
Lionel C. Bening, Tony M. Brewer,
Harry D. Foster, Jeffrey S. Quigley,
Robert A. Sussman, Paul F. Vogel and Aaron W. Wells,
``Physical Design of 0.35 $\mu m$ Gate Arrays
for Symmetric Multiprocessing Servers,''
{\em Hewlett-Packard Journal}, Article 16,
1997.
\bibitem{liu93}
S. Liu, K. Pan, M. Pedram, and A. M. Despain,
``Alleviating Routing Congestion by Combing Logic Resynthesis and
Linear Placement,''
{\em Proc. of European Conference on Design Automation},
pp. 578-582, 1993.
\bibitem{M90}
M. C. McFarland and T. J. Kowalski,
``Incorporating bottom-up design into hardware synthesis,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 9,
pp. 938-950, September 1990.
\bibitem{Mori95}
Y. Mori, V. G. Moshnyaga, H. Onodera and K. Tamaru,
``A performance-driven macro-block placer for architectural
evaluation of ASIC designs,''
{\em Proc. of the 8th IEEE Int. ASIC Conference and Exhibit},
pp. 233-236, 1995.
\bibitem{Murata96}
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani,
``VLSI module placement based on rectangle packing by sequence-pair,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 15,
pp. 1518-1524, December 1996.
\bibitem{Nakatake96}
S. Nakatake, K. Fujiyoshi, H. Murata,
and Y. Kajitani,
``Module placement on BSG-structure and IC layout applications,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 484-491, 1996.
\bibitem{Narayananan95}
V. Narayananan, D. Lapotin,
R. Gupta and G. Vijayan,
``PEPPER-a timing driven early floorplanner,''
{\em Proc. of Int. Conf. Computer Design},
pp. 230-235, 1995.
\bibitem{Natesan95}
V. Natesan and D. Bhatia,
``Performance driven placement for cell-based designs,''
{\em Proc. of the 8th IEEE Int. ASIC Conference and Exhibit},
pp. 237-240, 1995.
\bibitem{Ng89}
C. Ng, S. Ashtaputre, E. Chambers,
K.-H. Do, S.-T. Hui, R. Mody and D. Wong,
``A hierarchical floor-planning, placement, and
routing tool for sea-of-gates designs,''
{\em Proc. of IEEE Custom Integrated Circuits Conference},
pp. 3.3/1-3.3/4, 1989.
\bibitem{nijs97}
R. X. T. Nijssen and C. A. J. van Eijk,
``Regular Layout Generation of Logically Optimized Datapaths,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 42-47, 1997.
\bibitem{Odawara87}
Gotaro Odawara, Takahisa Hiraide and Osamu Nishina,
``Partitioning and placement technique for CMOS gate arrays,''
{\em IEEE Trans. on Computer-Aided Design}, vol.CAD-6,
pp.355-363, May 1987.
\bibitem{Otten98}
Ralph H.J.M. Otten and Robert K. Brayton
``Planning for Performance,''
{\em Proc. of the 35th Design Automation Conference},
pp. 122-127, 1998.
\bibitem{Prasitjutrakul90}
S. Parasitjutrakul and W. J. Kubitz,
``A timing-driven global router for custom chip design,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 48-51, 1990.
\bibitem{PeDh91}
M. Pedram and N. Bhat,
``Layout Driven Logic Restructuring/Decomposition,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 134-137, 1991.
\bibitem{PeDh912}
M. Pedram and N. Bhat,
``Layout Driven Technology Mapping,''
{\em Proc. of the 28th Design Automation Conference}, pp. 99-105, 1991.
\bibitem{pi98}
L. Pileggi, J. Cong, S. Otto and A. Yang,
``Timing Metrics for Phsical Design of Deep Sub-micron Technologies,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 28-33, 1998.
\bibitem{prea88}
B. T. Preas and M. J. Lorenzetti,
{\em Physical Design Automation of VLSI Systems},
Benjamin Cummings, Menlo Park, CA., 1988.
\bibitem{qui75}
N. R. Quinn,
``The Placement Problem as Viewed from the Physics of Classical
Mechanics,''
{\em Proc. of the 12th Design Automation Conference},
pp. 173-178, 1975.
\bibitem{Quinn79}
N. Quinn and M. Breuer,
``A force directed component placement procedure for printed circuit
boards,''
{\em Proc. of IEEE Trans. on CAS}, vol. CAS-26,
pp. 377-388, 1979.
\bibitem{Riess95}
B. M. Riess, and G. G. Ettelt,
``SPEED: fast and efficient timing driven placement,''
{\em Proc. of IEEE Int. Symp. on Circuits and Systems},
pp. 377-380, 1995.
\bibitem{Rim94}
M. Rim, A. Majumdar, R. Jain and R. De Leone,
``Optimal and Heuristic Algorithms for Solving the
Binding Problem,''
{\em IEEE Trans. on VLSI Systems}, vol. 2,
pp. 211-225, 1994.
\bibitem{Sait95}
S. M. Sait, H. Youssef,
K. Nassar and M. S. T. Benton,
``Timing driven genetic algorithm for standard-cell placement,''
{\em Proc. of IEEE 14th Int. Phoenix Conference on Computers
and Communications},
pp. 403-409, 1995.
\bibitem{Salek98}
Amir H. Salek, Jinan Lou and Massoud Pedram,
``A DSM Design Flow: Putting Floorplanning, Technology-Mapping,
and Gate-Placement Together,''
{\em Proc. of the 35th Design Automation Conference},
pp. 128-133, 1998.
\bibitem{Salek99}
Amir H. Salek, Jinan Lou and Massoud Pedram,
``MERLIN: Semi-Order-Independent Hierarchical Buffered
Routing Tree Generation Using Local Neighborhood Search,''
{\em Proc. of the 36th Design Automation Conference},
pp. 472-478, 1999.
\bibitem{Salek991}
Amir H. Salek, Jinan Lou and Massoud Pedram,
``An Integrated Logical and Physical Design flow
for Deep Submicron Circuit,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 18, No. 9,
pp. 1305-1315, September 1999.
\bibitem{Sapatnekar94}
S. Sapatnekar,
``RC Interconnect Optimization under the Elmore Delay Model,''
{\em Proc. of the 31th Design Automation Conference},
pp. 387-391, 1994.
\bibitem{Sau93}
G. Saucier, D. Brasen, J. P. Hiol,
``Partitioning with cone structures,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 236-239, 1993.
\bibitem{Sch72}
D. M. Schuler and E. G. Ulrich,
``Clustering and linear placement,''
{\em Proc. of the 9th Design Automation Conference},
pp.412-419, 1972.
\bibitem{Sentovich92}
E. M. Sentovich, et al.,
``SIS : A System for Sequential Circuit Synthesis,''
Department of Electrical Engineering and Computer Science,
UC Berkeley,May 1992.
\bibitem{sher95}
N. Sherwani,
{\em Algorithms for VLSI Physical Design Automation},
2nd ed., Kluwer Academic Publishers, 1995.
\bibitem{Soyata94}
T. Soyata and E. Friedman,
``Retiming with non-zero clock skew, variable register and interconnect
delay,''
{\em Proceeding of IEEE International Conference on Computer-Aided
Design},
November, 1994.
\bibitem{Sten97}
G. Stenz, B. M. Riess, B. Rohfleisch, F. M. Johannes,
``Timing Driven Placement in Interaction with Netlist Transformations,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 36-41, 1997.
\bibitem{su_ispd98}
H.-P. Su, Allen C.-H Wu and Y.-L. Lin,
``Performance-Driven Soft-Macro Clustering and Placement
by Preserving HDL Design Hierarchy,''
{\em Proc. of Int. Symp. on Physical Design}, pp. 12-17, 1998.
\bibitem{su_dac99}
H.-P. Su, Allen C.-H. Wu And Y.-L. Lin,
``A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip
Floorplanning,''
{\em Proc. of the 36th Design Automation Conference}, 1999.
\bibitem{su_tcad99}
H.-P. Su, Allen C.-H. Wu and Y.-L. Lin,
``A Timing-Driven Soft-Macro Placement and Resynthesis Method
in Interaction with Chip Floorplanning,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 18, No. 4.
April, 1999.
\bibitem{Wern95}
Wern Jieh Sun and C. Sechen,
``Efficient and effective placement for very large circuits,''
{\em IEEE Trans. on Computer-Aided Design}, vol. 143,
pp. 349-359, March,
1995.
\bibitem{Sutanthavibul90}
S. Sutanthavibul and E. Shragowitz
``An adaptive timing-driven placement for high VLSIs,''
{\em Proc. of the 27th Design Automation Conference},
pp. 90-95, 1990.
\bibitem{Sutanthavibul93}
S. Sutanthavibul, E. Shragowitz and R.-B. Lin,
``An adaptive timing-driven placement for high performance VLSIs,''
{\em IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems}, vol. 12,
pp. 1488-1498, October
1993.
\bibitem{Swartz90}
W. Swartz and C. Sechen,
``New algorithms for the placement and routing of macro cells,''{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 336-339, 1990.
\bibitem{Sylvester98}
Dennis Sylvester and Kurt Keutzer,
``Getting to the Bottom of Deep Sub-micron,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 203-211, 1998.
\bibitem{Tarafdar98}
Shantanu Tarafdar, Miram Leeser and Zixin Yin,
``Integrating Floorplanning In Data-Transfer Based High-Level
Synthesis,''
{\em Proc. of Int. Conf. Computer-Aided Design},
pp. 412-417, 1998.
\bibitem{Telle94}
G. E. Telle, D. A. Knol and M. Sarrafzadeh,
``A performance-driven placement technique based on a new
budgeting criterion,''
{\em Proc. of IEEE Int. Symp. on Circuits and Systems},
pp. 504-507, 1996.
\bibitem{Tsay88}
R.-S. Tsay, E. S. Kuh and C.-P. Hsu,
``PROUD: A fast sea-of-gates placement algorithm,''
{\em ACM/IEEE DAC},
pp. 318-323, 1988.
\bibitem{TsLi95}
Y.-W. Tsay and Y.-L. Lin,
``A Row-Based Cell Placement Method That Utilizes Circuit Structural
Properties,''
{\em IEEE Trans. on Computer-Aided Design}, vol.14, No. 3,
pp. 393-397, March 1995.
\bibitem{Ts97}
Y.-W. Tsay, W.-J. Fang, Allen C.-H. Wu, and Y.-L. Lin,
``Preserving HDL Synthesis Hierarchy for Cell Placement,''
{\em Proc. of Int. Symp. on Physical Design},
pp. 169-174, 1997.
\bibitem{Tseng98}
Hsiao-Ping Tseng, Louis Scheffer and Carl Sechen,
``Timing and Crosstalk Driven Area Routing,''
{\em Proc. of the 35th Design Automation Conference},
pp. 378-381, 1998.
\bibitem{Vaishnav93}
H. Vaishnav and M. Pderam,
``Routability-Driven Fanout Optimization,''
{\em Proc. of the 30th Design Automation Conference},
pp. 230-235, 1993.
\bibitem{Vaishnav95}
H. Vaishnav and M. Pderam,
``Minimizing the Routing Cost During Logic
Extraction,''
{\em Proc. of the 32th Design Automation Conference},
pp. 70-75, 1995.
\bibitem{Venkatesh95}
S. V. Venkatesh
``Hierarchical timing-driven floorplanning and place and route
using a timing budgeter,''
{\em Proc. of IEEE Custom Integrated Circuits Conference},
pp. 469-472, 1995.
\bibitem{Vittal94}
A. Vittal and M. Marek-Sadowska,
``Minimal Delay Interconnect Design Using Alphabertic Trees,''
{\em Proc. of the 31th Design Automation Conference},
pp. 392-396, 1994.
\bibitem{Wei91}
Y. C. Wei and C.K. Cheng,
``Ratio cut partitioning for hierarchical designs,''
{\em IEEE Trans. on Computer-Aided Design}, vol.CAD-10,
pp. 911-921, July 1991.
\bibitem{Weng91}
J.-P. Weng and A. C. Parker,
``3D Scheduling: High Level Synthesis with Floorplanning,''
{\em Proc. of the 28th Design Automation Conference},
pp. 668-673, 1991.
\bibitem{Wu92}
Ching-Ting Wu, Lim A. and Du D.
``An Effective Timing-Driven Placement Algorithm For
Macro Cells,''
{\em Porc. of 5th Int. Conference on VLSI Design},
pp. 31-36, 1992.
\bibitem{Youssef95}
H. Youssef, S. M. Sait and K. J. Alfarra,
``Timing influenced force directed floorplanning,''
{\em Proc. of European Conference on Design Automation},
pp. 156-161, 1995.
\bibitem{Zhou99}
H. Zhou and D. F. Wang
``Global Routing with Crosstalk Consraints,''
{\em IEEE Trans. on Computer-Aided Design,} vol. 18,
pp. 1683-1688, November, 1999.
\bibitem{r1} ``HDL Compiler for Verilog Reference Manual Version 3.4b'',
Synopsys, Mountain View, CA. 1996.
\bibitem{r3} ``Silicon Ensemble Reference Manual Version 5.0'', Cadence,
San Jose, CA, 1996.
\bibitem{opus} ``Layout Editor Reference Manual Version 4.3.4'', Cadence,
San Jose, CA, 1997.
\bibitem{r34} ``Apollo Reference Manual Version 2.1.2'', AVANT!,
Fremont, CA, 1999.
\bibitem{r4} ``STAR-RC Reference Manual Version 2.2'', AVANT!,
Fremont, CA, 1997.
\bibitem{r5} ``STAR-DC Reference Manual Version 2.1.2'', AVANT!,
Fremont, CA, 1996.
\bibitem{Np84} N.P. Jouppi,
``Timing Verification and Performance Improvement of MOS VLSI
Designs,''
{\em PhD thesis, Standard University, Standford, CA}, OCT. 1984.
\bibitem{lib} ``TSMC ASIC Data Book TCB670'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1997
\bibitem{lib1} ``TSMC DSD Data Book ACB872'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1998
\bibitem{TSMC_PAR05} ``TSMC Design Rule of 0.5 $\mu m$ process'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1996
\bibitem{TSMC_PAR035} ``TSMC Design Rule of 0.35 $\mu m$ process'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1997
\bibitem{TSMC_PAR025} ``TSMC Design Rule of 0.25 $\mu m$ process'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1998
\bibitem{TSMC_PAR018} ``TSMC Design Rule of 0.18 $\mu m$ process'', Taiwan Semiconductor
Manufacturing Company, Ltd. Hsinchu, Taiwan, R.O.C. 1999
\bibitem{SIA97} Semiconductor Industrial Alliance
{\em National Technology Roadmap for Semiconductors},
1997.

全文公開日期 本全文未授權公開 (校內網路)
全文公開日期 本全文未授權公開 (校外網路)
全文公開日期 本全文未授權公開 (國家圖書館：臺灣博碩士論文系統)