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研究生： 陳世旻
Shih-Min Chen
論文名稱： 8×8 分時多工交換機和8B/10B編解碼器的設計與實現
Design and Implementation of 8x8 Time division Multiplexing (TDM) Switch with 8B/10B CODEC
指導教授： 馮開明
Kai-Min Feng
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 通訊工程研究所
Communications Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 63
中文關鍵詞： 分時多工交換機 、編解碼器 、負載平衡信箱交換機 、記憶體交換架構
外文關鍵詞： TDM switch, CODEC, mailbox switch, share memory switch
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    • 目前市場上的大多數交換機(例如，乙太交換機)是基於所謂的分享記憶體交換架構。在這樣的一個交換架構，封包被儲存並且分送是在一個共用記憶體的交換架構。以目前光纖的速度優點，在記憶體連接速度便成為共用記憶體交換架構的瓶頸。而我們為了取得高速，必須使用一個與相似緩衝加快速度的交換架構。有一種被稱為輸入緩衝的交換架構的方法，它是在一個（橫桿）交換機結構的前面有並行的緩衝器。在一個有輸入緩衝器的交換過程中，時間同步並且安排，所以封包可以被並聯傳送以相同大小的方式。因為有多個緩衝區（儲存器），輸入緩衝交換機的關鍵問題是解決並行儲存器進入的衝突。它在任何非均勻化的交通流下使用較小技術的假設便可使交換機的處理能力達到100％。
    一個在大學追求發展卓越計畫的主要項目，就是設計跟實作可以在高速的光纖輸下可擴充的高速交換機。依據負載平衡信箱交換機的理論，使用8x8分時多工交換機經由遞迴的建構便可達到超高速的交換能力。我们已經設計了一個可以工作的30Gbps分時多工加上8/10B編/解碼的交換機使用.18um COMS的製程。8×8分時多工交換機（TDM）的ICs設計就是為了實現在信箱交換機架構上的一個交換機結構的模組。這是一個協定於封包和小細胞交換應用的獨立交換機。最後我們會有完整的測試報告以及相關的討論。

    The 8x8 Time Division Multiplexing (TDM) Switch ICs are designed to implement a building module of the switch fabric based on mailbox switch architecture. The proposed load-balanced mailbox switch can achieve ultra high speed switch capability with 8x8 TDM switch via recursive construction. An 8x8 TDM switch could be constructed recursively from the proposed switch module to achieve switching capacity of hundred gigabits per second or higher. There was an 8x8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet application. A novel testing circuit was also implemented to easily verify switching result. Our results showed a 20 Gbps switching capacity for the 8x8 TDM switch with parallel input and output ports. All implementation were based on the 0.18μm CMOS technology.

    CONTENTS Chinese Abstract………………………………………………………Ⅰ English Abstract………………………………………………………Ⅱ Acknowledgments……………………………………………………..Ⅲ Contents………………………………………………………………..Ⅳ CHAPTER 1 Introduction 1 1.1 Current Development of Related Research........................................................... 1 1.2 Research Motivation....................................................................... 2 CHAPTER 2 Overall architecture 6 2.1 TDM switch features……………..................................................... 6 2.2 Overall Architecture........................................................................................ 7 2.3 Interface Signals………………………............................................. 8 CHAPTER 3 Sub-block architecture 10 3.1 An 8x8 Symmetric TDM Switch Module………………........................... 10 3.1.1 A 2×2 Switch Block Architecture...........................................……………11 3.1.2 The Switch Pattern Generation Block........................................................ 11 3.2 CODEC architecture……………………….......................................................16 3.2.1 Encoder architecture..........................................................................……..17 3.2.2 Decoder architecture…………...……………………………................….19 3.3 Pattern Driver and Pattern Monitor Block.......................................................... 20 CHAPTER 4 Implementation of an 8x8 TDM switch with 8/10B codec IC 21 4.1 Description of design block.....................................……………….....................21 4.2 Design flow…………........................................................................................ 22 4.2.1 Synthesis with design complier…………….........................................….22 4.2.2 Gate-level simulation................................................................. 23 4.2.3 Design for Testability with DFT compiler and TetraMax……..................24 4.2.4 Place & route…………………………………………………24 4.2.5 Static timing analysis…………………………………………………25 4.3 Simulation result............................................................................................... 25 4.3.1 Functional simulation................................................................................ 25 4.3.2 Gate level simulation…………………….............................................. 27 4.3.3 Post-Layout Gate Level Simulation…………………………………29 4.3.4 Monitor file compared with input file………………………………31 4.3.5 Overall chip layout and performance summary………………….……32 CHAPTER 5 Testing result and discussion 33 5.1 Testing set up on ATE.....................................……………….......................... 33 5.1.1 Place & route on the board………………………………………………… 33 5.1.2 Pin list mapping…………………………………………………………….34 5.1.3 Voltage level setup………………………………………………………….34 5.1.4 Timing setup………….……………………...……………………………..34 5.1.5 Vector file prepare……..……………………………………………………35 5.2 Testing result.......................................................................................................36 5.2.1 Pattern driver with monitor load mode…………………………..………….36 5.2.2 Pattern driver with output data loads mode….…….………………………..38 5.2.3 TDM switch mode……….…………………………………………………..39 5.2.4 TDM plus CODEC mode………..………………………………………….39 5.2.5 Signal pattern generator mode……...………………………………………..40 5.3 Result table……………………………………………………………………..50 5.4 Discussion……………………………………………………………………...50 5.4.1 Pad selects consideration……………………………………………………51 5.4.2 Adding the high loading capacitance into the post-layout simulation………54 5.4.3 Adding high loading capacitance on the P8A model………...………………54 5.4.4 Layout strap consideration……………………..……………………………57 5.4.5 Testing with our PCB design………………………………………………...58 CHAPTER 6 Conclusion 61 Reference................................................................................................................. 62

    [1]. C. S. Chang, D. S. Lee and Y. S. Jou, “Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering,” Computer Communications, Vol. 25, pp. 611-622, 2002
    [2]. C. S. Chang, D. S. Lee and C. M. Lien, “Load balanced Birkhoff-von Neumann switch, part II: Multi-stage buffering,” Computer Communications, Vol. 25, pp. 623-634, 2002
    [3]. C. S. Chang, D. S. Lee and Y. J. Shih, “Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets,” INFORCOM’2004, pp.1995 - 2006, Volume: 3, ISSN: 0743-166X, March 2004
    [4]. Widmer, A.X&Franaszek, P.A., A DC-Balanced, Partitioned-Block, 8b/10b Transmission Code. IBM J. Res. Develop ., Vol. 27, No. 5. September 1983.
    [5]. Arekapudi, S., Shang-Tse Chuang, Keslassy, I., McKeown, N., “Using hardware to configure a load-balanced switch”, Micro, IEEE, Volume 25, Issue 1, Jan.-Feb. 2005 pp. 70 – 78
    [6]. Yorozu, S.; Hashimoto, Y.; Kameda, Y.; Terai, H.; Fujimaki, A.; Yoshikawa, N., ” A 40 GHz clock 160 Gb/s 4/spl times/4 switch circuit using single flux quantum technology for high-speed packet switching systems”, High Performance Switching and Routing, 2004. HPSR. 2004 Workshop on 2004 pp.20-23
    [7]. T. Anderson, S. Owicki, J. Saxes and C. Thacker, “High speed switch scheduling for local area networks, ” ACM Trans. On Computer System, Vol. 11, pp. 319-352, 1993.
    [8]. G. Birkhoff, “Tres observaciones sobre el algebra, ” Univ. Nac. Tucuman Rev. Ser. A, Vol, 5, pp. 147-151, 1946.

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