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研究生: 尤瑞辰
Yu, Ruey-Chern
論文名稱: 基於卷積神經網絡與神經網絡搜尋最佳化的靜態電路壓降預測
A CNN-Based Approach for Static IR Drop Prediction with Neural Architecture Search Optimization
指導教授: 麥偉基
Mak, Wai-Kei
口試委員: 王廷基
Wang, Ting-Chi
陳宏明
Chen, Hung-Ming
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2024
畢業學年度: 113
語文別: 英文
論文頁數: 33
中文關鍵詞: 靜態電路壓降卷積神經網路神經網絡搜尋最佳化
外文關鍵詞: Static IR Drop, CNN, Neural Architecture Search
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  • 隨著半導體製程的進步,電源完整性問題是積體電路實體設計中需要考慮的一環。
    電路壓降,屬於電源完整性的其中一個項目,指的是電流通過電源供應網路時,由於
    金屬導線電阻引起的電路壓降,過高的電壓損耗會使得訊號及電源傳遞到電晶體時無
    法正確的驅動,引起電路功能完整性的問題,因此在設計規則檢查中占有重要地位。
    傳統上,要得到精確的靜態電路壓降值需要等到電路繞線完畢,使用克希荷夫電壓定
    律進行節點分析來得知電路壓降的狀況。然而數萬個節點會使得聯立方程組過於龐大,
    求精確解的過程過於耗時。在本論文中,我們提出一個使用卷積神積網路的機器學習
    模型和改進的資料處理,在尚未繞線前,能夠預測出當前的靜態電路壓降的方法,相
    對先前的研究,我們能以更好的平均絕對誤差及 F1 分數,有效地預測靜態電路壓降。


    As the semiconductor manufacturing process advances, power integrity issues
    have become an important design rule check during physical design. Voltage drop,
    part of power integrity, refers to the voltage drop caused by the resistance of metal
    conductors in the power delivery network when current flows from the power pad
    to the transistor. Excessive voltage drops can prevent signals from correctly driving
    the transistors, leading to functional behavior issues. Hence, it holds a significant
    place in design rule checks. Traditionally, obtaining precise static voltage drop
    values requires completing the circuit routing and using Kirchhoff’s voltage law
    for node analysis to identify where voltage drop issues occur. However, analyzing
    tens of millions of nodes results in a system of equations that is too large, making
    the time to find an exact solution excessively long. In this thesis, we propose a
    machine learning model using convolutional neural networks and improved data
    extraction to predict static voltage drop in the layout design before the routing stage
    once we have the placement result and the powerplan. Compare to the previous
    work, we can have a better prediction quality in terms of both MAE and F1 score.

    誌謝 摘要 i Abstract ii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Background 5 2.1 Power Delivery Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Flip-chip design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 IR Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Convolutional Neural Network . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Proposed Approach 9 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Data Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1 Effective Distance Map . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.2 Power Delivery Network Map . . . . . . . . . . . . . . . . . . . . . . 11 iii 3.2.3 Current Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Learning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.1 U-Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3.2 Neural Architecture Search . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Experimental Results 21 4.1 Experimental Environment and Benchmarks . . . . . . . . . . . . . . . . . . . 21 4.1.1 Data Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Conclusion 29

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