反轉式與無接面式奈米薄片通道多閘極電晶體與非揮發性記憶體之研究

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研究生：	林育如 Lin, Yu-Ru
論文名稱：	反轉式與無接面式奈米薄片通道多閘極電晶體與非揮發性記憶體之研究 Study of Inversion and Junctionless Nanosheet Channel on Multi-gate Field Effect Transistors and Non-Volatile Memory Devices
指導教授：	吳永俊 Wu, Yung-Chun 林育賢 Lin, Yu-Hsien
口試委員:	劉柏村 Liu, Po-Tsun 張廖貴術 ChangLiao, Kuei-Shu 巫勇賢 Wu, Yung-Hsien
學位類別：	博士 Doctor
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2019
畢業學年度：	107
語文別：	英文
論文頁數：	134
中文關鍵詞：	無接面式場效電晶體、堆疊式奈米薄片、非揮發性記憶體、環繞式閘極
外文關鍵詞：	Junctionless Field Effect Transistor, Stacked Nanosheet
相關次數：	點閱：2 下載：0
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因應市場需求，電子產品不僅要追求高速、高效能，必須兼備低耗電與低成本。現今全球各大半導體廠面對元件持續的微縮，製程技術或達到良好元件性能的困難度已隨之上升，單純地縮減通道長度或將介電層厚度持續降低已無法得到良好的電流開關比、高電流驅動力、低漏電和極佳可靠度的需求，因此開發出一個滿足高性能與可擴展性的目標相當重要。本論文探討反轉式與無接面式奈米薄片通道多閘極電晶體與非揮發性記憶體，以符合未來電晶體技術的可能性。本論文共分為三個部份，(1)超薄奈米薄片無接面式場效電晶體，(2)堆疊式奈米薄片通道之場效電晶體，(3)氮化物介面缺陷應用於SONOS型非揮發性記憶體。
第一部份主要以奈米薄片通道無接面式電晶體為主，首先探討鎳矽化物應用於無接面式電晶體接觸窗口，對於鎳矽化物薄膜，採用兩步驟退火和鈦覆蓋層形成具有均勻及低片電阻的鎳矽化物薄膜，相較於接觸窗口無鎳矽化物元件，此鎳矽化物於接觸窗口元件具有更高的驅動電流和低電阻。此外，第一部份亦提出奈米薄片無接面式電晶體搭配混合式反參雜通道結構，藉由不同型參雜之結構設計，在P型與N型介面產生空乏區，使通道等效厚度變薄，以獲得較佳的關閉特性，此外，藉由模擬結果得知，溝槽結構對於此元件為最重要的關鍵因素。
第二部份提出以堆疊式奈米薄片通道的電晶體，首先提出堆疊奈米薄片無接面式電晶體，比較單根與雙根通道結構，以及多閘極與環繞式閘極結構之特性，由實驗結果得知，堆疊式奈米薄片無接面式環繞式閘極電晶體有較佳的特性以及溫度設計靈活性，進一步利用三維半導體元件模擬技術，提出堆疊奈米薄片無接面式電晶體結合混合式反參雜通道結構，為堆疊無接面式電晶體提供另一個應用。接著，提出堆疊奈米薄片反轉式閘極與環繞式閘極電晶體，並比較平板通道與奈米薄片通道之特性。最後，探討無接面式及反轉式堆疊通道電晶體實驗分析。簡而言之，堆疊通道電晶體具有成為微縮矽電晶體的潛力候選結構，並可能用於先進三維堆疊的應用。
最後，提出以雙層氮化物中間介面缺陷作為額外電荷儲存層的溝槽結構無接面式非揮發性記憶體，此記憶體元件相較於傳統單層氮化物非揮發性記憶體具有較快的寫入抹除速度、較佳的重覆抹寫耐久度以及極佳的保存能力。進一步，提出奈米薄片通道環繞式閘極結構非揮發性記憶體於雙層氮化物中間介面缺陷及矽奈米點作為電荷儲存層的比較，實驗結果得知雙層氮化物為電荷儲存層，經過104次抹寫後仍具有86%記憶窗口，並利用溫度加速測試方法，推算此記憶體結構經過十年後仍可保存42%的記憶窗口。此雙層氮化物介面缺陷具有較佳的均勻性，除了有效提升記憶體可靠度特性，更有機會可以整合於未來三維堆疊之記憶體結構。

In response to market demands, the electronic products pursue not only the higher speed and better performance, but also less power consumption and lower cost. The Semiconductor ICs manufacturing companies still follow Moore's law to scaling. The accompanying difficulties in either developing required process technology or enhancing device performance are also increased. Simply shrinking the channel length and/or the dielectric thickness can no longer realize the excellent switching ratio, high driving capability, low leakage current and acceptable reliability. Therefore, it is important to develop a target that suffices high performance and scalability. This thesis investigates the inversion and junctionless nanosheet channel with multi-gate field-effect transistor and non-volatile memory for the possibility of future transistor technology. This thesis is divided into three parts to demonstrate the (1) ultra-thin nanosheet junctionless field-effect transistor, (2) stacked nanosheet channels field-effect transistor, (3) nitride interface defects in SONOS-type non-volatile memory.
In the first part, an ultra-thin poly-Si nanosheet junctionless field-effect transistor with nickel silicide contact was demonstrated successfully. For the nickel silicide film, two-step annealing and a Titanium capping layer were adopted to form an ultra-thin uniform nickel silicide film with low sheet resistance. The junctionless device with nickel silicide contact exhibited higher driving current, and low resistance than the junctionless device the without nickel silicide contact. Moreover, the trench and raised source and drain structure with gate-all-around based on the p-type/n-type hybrid nanosheet junctionless field-effect transistor was also demonstrated. The junctionless device with hybrid structure can also provide depletion region between p-type and n-type interface to electrically reduce channel thickness and turn off the device easily. Notably, as the simulation result, the trench structure is the most important factor of this device.
In the second part, the stacked nanosheet channels field-effect transistors had been demonstrated. At first, this part comprehensively investigated the stacked nanosheet-type channels based on the junctionless field-effect transistors, including single and stacked channel structures, and multi-gate and gate-all-around structures. The stacked gate-all-around junctionless field-effect transistors exhibited superior performance and excellent temperature design flexibility. Furthermore, this part also provided the hybrid p-type/n-type/p-type stacked channels device based on the junctionless field-effect transistor by using 3D TCAD simulated analysis for the stacked structure another application. Second, the stacked nanosheet-type double-channels with multi-gate and gate-all-around inversion mode field-effect transistors were also demonstrated. For comparison, the stacked planar device which top view width is equal to the stacked nanosheet device was fabricated. Final, this part demonstrated an experimental comparative analysis of the stacked nanosheet channels integrated junctionless and inversion mode field-effect transistors in Si-based technology. Briefly, the stacked nanosheet channels field-effect transistor emerges as promising candidate for scaling down the Si FET and potentially uses in advanced 3-D stacked ICs applications.
In the final part, the junctionless field-effect transistor based on trench structure non-volatile memory with doubly stacked Si3N4 defect charge trapping layers had been demonstrated. The device exhibits high program/erase (P/E) speed, good endurance and excellent data retention at 85oC which achieve memory industry requirement. The silicon-oxide-nitride-nitride-oxide-silicon (SONNOS) and silicon-oxide-nitride-silicon -nanocrystals-nitride-oxide-silicon (SOncOS) nonvolatile memory based on nanosheets gate-all-around structure were further compared. The SONNOS and SOncOS devices exploit doubly stacked Si3N4 interface defects and silicon nanocrystals (Si-NCs) as charge trapping layers, respectively. Experimental results reveal that the SONNOS device retains 86% memory window after 104 program/erase cycles, and the memory window retains 42% of the originally stored charge after ten years. Such doubly stacked Si3N4 layers provide additional and uniform charge trapping sites in charge trapping layer, improving the memory performance of nonvolatile memory. This simple double stacked Si3N4 structure will be easily integrated in 3D NAND flash memory applications.

中文摘要    i
Abstract    iv
Acknowledgement    viii
Contents    ix
List of Figures    xiv
Chapter 1    1
Introduction    1
1-1  Challenges of Device Scaling and Opportunities    1
1-2　Device Structures in Advanced Field-Effect Transistor    3
1-2-1　Junctionless Field-Effect Transistor    3
1-2-2　Stacked Nanosheets Field-Effect Transistor    6
1-2-3　Multi-Gate Field-Effect Transistor    8
1-3　Non-volatile Memory    9
1-3-1　Mechanism of Non-volatile Memory    9
1-3-2　Fowler-Nordheim (FN) Tunneling Mechanism    10
1-3-3　Reliability of Nonvolatile Memory    11
1-4　Motivation    12
1-5　Organization of This Thesis    14
Chapter 2    15
Ultra-Thin Nanosheet Field-Effect Transistor    15
2-1　Ultra Thin Poly-Si Nanosheet Junctionless Field-Effect Transistor with Nickel Silicide Contact    15
2-1-1　Introduction and Literature Review    15
2-1-2　Silicide Film Analysis    17
2-1-3　Device Structure and Fabrication    21
2-1-4　Results and Discussion    22
2-1-5　Summary    26
2-2　Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure    27
2-2-1 Introduction and Literature Review    27
2-2-2　Device Structure and Fabrication    28
2-2-3　Simulation Approach    30
2-2-4　Results and Discussion    31
A.    Experimental Results    31
B.    Simulated Results    40
2-2-5　Summary    43
Chapter 3    44
Stacked Nanosheet Field-Effect Transistor    44
3-1　Comprehensive Study of Stacked Nanosheet-Type Channels Integrated Junctionless Mode Field-Effect Transistors    44
3-1-1　Introduction and Literature Review    44
3-1-2　Device Structure and Fabrication    45
3-1-3　Simulation Approach    47
3-1-4　Results and Discussion    48
A.　Comparison of the Single and Stacked Junctionless Field-Effect Transistors    48
B.　Simulated the Channel Dimensions and InterlayeroxideThickness    52
C.　Comparison of the Contact Structure based on stacked Junctionless Field-Effect Transistors    54
D.　Comparison of the Gate structure with Multi-Gate and Gate-All-Around    56
E.　Simulated the Stacked Junctionless Field-Effect Transistors with Hybrid Structure    60
3-1-5　Summary    63
3-2　Comprehensive Study of Stacked Nanosheet-Type Channels Integrated Inversion Mode Field-Effect Transistors    64
3-2-1　Introduction and Literature Review    64
3-2-2　Device Structure and Fabrication    65
3-2-3　Simulation Approach    67
3-2-4　Results and Discussion    68
A.　Comparison of the Channel structure with Nanosheets and Planar    68
B.　Comparison of the Gate structure with Multi-Gate and Gate-All-Around    73
C.　Comparison of Different Channel Dimensions    78
3-2-5　Summary    79
3-3　Comparsion of Stacked Nanosheet-Type Channels Based on Inversion and Junctionless Mode Field-Effect Transistors    80
3-3-1　Results and Discussion    80
3-3-2　Summary    83
Chapter 4    84
Nitride Interface Defects in SONOS-type Non-Volatile Memory    84
4-1　Artificial Defects in Si3N4 Enhance Nonvolatile Memory Performance of Ultra-Thin Body Poly-Si Junctionless Field-Effect Transistors    84
4-1-1　Introduction and Literature Review    84
4-1-2　Device Structure and Fabrication    85
4-1-3　Results and Discussion    86
4-1-4　Summary    93
4-2　Comparison With Nitride Interface Defects and Nanocrystals for Charge Trapping Layer Nanowire Gate-All-Around Nonvolatile Memory Performance    94
4-2-1　Introduction and Literature Review    94
4-2-2　Device Structure and Fabrication    95
4-2-3　Results and Discussion    97
4-2-4　Summary    107
Chapter 5    108
Conclusions    108
Reference    110
Curriculum Vitae    128
Publication List    129


                                

Chapter 1
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Chapter 2
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Chapter 3
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[3.17] Y. C. Cheng, H. B. Chen, C. Y. Chang, C. H. Cheng, Y. J. Shih, and Y. C. Wu, "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs," in 2016 IEEE Symposium on VLSI Technology, 2016, pp. 1-2. doi:10.1109/VLSIT.2016.7573429.
[3.18] Y. C. Cheng, H. B. Chen, C. S. Shao, J. J. Su, Y. C. Wu, C. Y. Chang, and T. C. Chang, "Performance enhancement of a novel P-type junctionless transistor using a hybrid poly-Si fin channel," in 2014 IEEE International Electron Devices Meeting, 2014, pp. 26.7.1-26.7.4. doi:10.1109/IEDM.2014.7047116.
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Chapter 4
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