研究生: |
陳貴祥 Gui-Xiang Chen |
---|---|
論文名稱: |
適用於IEEE 802.16-2004正交分頻多工通訊系統之基頻傳送接收機矽智產 A Baseband Transceiver IP for IEEE 802.16-2004 OFDM Communications |
指導教授: |
馬席彬
Hsi-Pin Ma |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2007 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 114 |
中文關鍵詞: | 矽智產 、正交分頻多工 、快速傅利葉轉換 、無線都會網路 |
外文關鍵詞: | SIP, OFDM, Fast Fourier Transform, WIMAX |
相關次數: | 點閱:2 下載:0 |
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在這篇論文中,提出了一個遵循IEEE 802.16-2004標準OFDM PHY的基頻傳送接收機矽智產設計。 此矽智產支援四種不同的調變方式:BPSK、QPSK、16-QAM以及64-QAM。此矽智產也支援1/32、1/16、1/8以及1/4等四種不同的CP長度比例。此矽智產使用20 MHz通道頻寬並且可以支援已被通道編碼後的資料速率最大多達92.16 Mbps。此一被提出的基頻傳送接收機矽智產包含好幾個功能,分別是時間同步(Timing Synchronization)、頻率同步(Frequency Synchronization)、快速傅利葉轉換(FFT)、通道估測(Channel Estimation)、等化(Equalization)、相位追蹤(Phase Tracking)、以及解調變(De-Modulation)。
此基頻傳送接收機矽智產的設計與驗證是從研究系統規格開始,包含提出系統架構、評估系統效能、邏輯電路設計、功能模擬、編碼風格檢查、程式碼覆蓋率分析、邏輯電路合成以及合成後的功能模擬。此外,此矽智產亦經由場效可程式邏輯閘陣列(FPGA)原型(FPGA Prototyping)的驗證。
當此基頻傳送接收機矽智產使用TSMC 合成0.18 微米1p 6m 的技術來合成邏輯電路時, 傳送機的最大操作時脈頻率可以達到40 MHz,而接收機的最大操作時脈頻率可以達到25 MHz。 傳送機和接收機的功率消耗分別約為9 mW 和75 mW。 此矽智產透過模擬和仿真的結果比對證明了功能的正確性,同時亦呈現了令人滿意的效能。
In this thesis, a SIP design and verification of a baseband transceiver that complies with IEEE 802.16-2004 standard OFDM PHY layer is presented.
The proposed baseband transceiver IP supports BPSK, QPSK, 16-QAM, and 64-QAM modulation as well as four different CP length ratio. The IP uses 20 MHz channel bandwidth and supports maximum coded data rate up to 92.16 Mbps. The proposed baseband transceiver IP consists of several functional blocks such as timing synchronization, frequency synchronization, FFT, channel estimation, equalization, phase tracking, and demodulation.
The design flow of the baseband transceiver IP starts from system specification study, architecture de‾nition, and performance evaluation. The following steps consists of logic design, functional simulation, coding style check, code coverage analysis. The next steps are logic synthesis and gate-level simulation. Last and most specially of all steps are the FPGA prototyping and emulation.
The baseband transceiver IP is synthesized in TSMC 0.13 ¹m 1p6m technology. The maximum operating clock rate of transmitter is 40 MHz, and the maximum operating
clock rate of receiver is 25 MHz. The power consumption of transmitter and receiver are about 9 mW and 75 mW respectively. Simulation results and emulation results present correct function and satisfactory performance of the baseband transceiver IP.
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