隨著製程技術的進步，許多新型元件結構的誕生，對於元件的特性如導通電阻，崩潰電壓和元件可靠度的需求也日益增加。在本論文中我們提出了三種不同結構的整合型金氧半場效電晶體對高功率電晶體的元件特性與熱載子退化效應作一番完整的探討。
由於二氧化矽(SiO2)有比較低介電常數和較高崩潰電場的特性，因此，我們提出一個新型的結構，利用介電材料(SiO2)來調變汲極延伸型金氧半電晶體的漂移區電場以增加崩潰電壓。利用先進技術的互補式金氧半電晶體(CMOS)製程，藉由更改淺層溝渠隔離技術(STI)的光罩佈局，我們成功的設計出在20V崩潰電壓的應用範圍下，擁有較低的導通電阻(RON, SP)。從實際的量測數據顯示，元件的崩潰電壓可以隨著漂移區裡的介電質大小來調整。也就是說，可以提供類比IC元件設計者擁有多重電壓的選擇性。
為了提昇元件的耐壓能力，傳統的方法是在漂移區置入STI，可以有效疏解閘極邊緣的高電場來增加崩潰電壓。然而，導通電阻是高壓元件用於Switch電路時效能的重要參數。在希望可以降低高功率電晶體的導通損耗(conduction loss)情況下，因此我們所設計的元件須具有低的導通電阻。對於0.25μm N通道的橫向擴散金屬氧化場效電晶體 (LDMOSFET)，在不影響元件的崩潰電壓與製程步驟的條件下，藉由更改淺層溝渠隔離技術(STI)的光罩佈局，我們提出一個可以成功地降低導通電阻20%的方法:將Z方向的STI設計成柵欄式的架構，同時搭配CMOS製程中的LDD(Lightly Doped Drain)摻雜，可以縮短電流的導通路徑來獲得較低的導通電阻和較高的驅動電流。
研究顯示，浮接式導體(floating field conductors)可以有效改善元件的特性。因此我們利用在汲極延伸型金氧半場效電晶體漂移區研究浮接式多晶矽的效應。由實驗結果與二維製程及電性模擬分析，我們探討浮接式多晶矽金氧半場效電晶體(FPS-LDMOS)的元件特性與可靠度分析。另一方面，為了避免Kirk effect發生在高的閘極偏壓下導致加速元件的退化。我們發現適當的設計浮接式多晶矽的大小與位置，可以有效的控制元件的基體電流。同時也發現傳統的第一個基體電流的峰值，可以當作是熱載子退化效應的指標。
最後，我們針對0.25μm P型橫向擴散金屬氧化物電晶體(P-LDMOS)，分析元件的熱載子可靠度問題。我們探討在熱載子測試中，P-LDMOS的線性區電流(IDLIN)的退化行為。發現經過熱載子測試後第一瞬間(不大於50ms)的線性區電流(IDLIN)會異常增加，接著之後，電流幾乎沒有退化或改變的行為。藉由二維的電性模擬，我們證實是因為熱電子注入STI邊緣，造成第一瞬間異常的線性區電流增加。實驗結果發現，線性區電流的增加量是與最大撞擊游離化產生速率(Max. IIGR)的區域到熱電子注入STI邊緣的距離是成正比關係。然而，針對元件退化會回復(Recovery)的特性，經過高溫、高壓環境測試，我們發現注入的熱電子是非常穩定的。

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