In this thesis, we study the two major topics of semiconductor devices - Scaling down and Reliability and ESD - by TCAD simulation and physical implementation.
For devices scaling down, we focus on silicidation process and multigate application. In silicidation, our study demonstrates that MOSFETs with increasing leakages and decreasing driving capability are correlated to the redistribution of the silicidation-induced doping which results in the devices with poly-depletion and flat band voltage shift. For scaling down with multi-gate approaches, we study the proposed LOCOS finFETs. Our simulation shows that the interspace oxide of LOCOS finFETs offers desired electrical isolation and its limited Si connection provides good thermal dissipation from the fin to the bulk. Therefore, LOCOS finFETs have nearly no self-heating under high output current condition and maintain low leakage current at off state.
About the reliability and ESD issues, we are interested in the current (or voltage) stress behaviors and failure mechanism of several ESD devices: poly-Si diodes, poly-Si TFTs and SCRs. For the poly-si devices, we studied their behaviors under extremely high current condition. Theoretical analysis demonstrates that the open-circuit failure modes of poly-Si dvices are caused by the electrothermal-enhanced migration of disordered silicon atoms at grain boundaries.
For the SCRs, we study their carrier distribution under different states. Our simulation results show that the voltage drop between the anode and the cathode highly depends on the minority carrier distribution in well regions. Therefore, to control the minority carrier distribution by different topological layout and doping concentration, one can manipulate the behavior of SCR.

本論文主要藉由半導體工藝電腦輔助設計模擬(TCAD)及晶片實作研究半導體元件的兩大主題—(1)尺寸縮小及(2)可靠性與靜電放電現象(ESD)。
在元件尺寸縮小方面，我們主要研究矽化 (silicidation) 製程與多閘極的應用。關於矽化製程，我們的研究結果顯示金氧半場效電晶體 (MOSFET) 的漸增漏電流及漸減的驅動能力與矽化製程引起的參雜改變有關。且此變化的參雜造成多晶矽閘的空乏區成型以及平帶電壓改變。關於多閘極的應用，我們研究區間氧化鰭型場效電晶體 (LOCOS finFET)。我們的研究結果顯示此種鰭型場效電晶體的區間氧化物提供有效電性阻隔，而其於鰭部與基板間的有限矽聯結則提供良好的熱傳遞。因此區間氧化鰭型場效電晶體於高輸出電流下幾乎沒有明顯溫度增加並於關閉狀態時保持低漏電流。
在可靠性與靜電放電現象方面，我們主要研究幾個靜電放電保護元件 (多晶矽元件與矽控變阻器 (SCR) ) 於大電流或高電壓下的行為及其失效故障機制。我們的結果顯示多晶矽元件於極端大電流下展現開路故障模式，且此結果可歸因於在多晶矽微粒邊界上的矽原子受電熱效應所增強的原子遷移所導致。
關於矽控變阻器方面，我們研究其在不同工作狀態下的載子分佈。我們的模擬顯示矽控變阻器在陽極及陰極間的壓降與井部的少數載子分佈有高度相關。因此，藉由元件的不同空間佈局及參雜濃度條整，我們可以調控矽控變阻器的動作。

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