在這篇論文中，我們將分別就面積與效能這兩大要素，去評估層級式以及混合式之可程式規劃陣列之間的優劣表現。在面積評估方面，我們發現混合式之可程式規劃陣列僅僅只比階層式之可程式規劃陣列小了百分之零點零八。而在效能評估上，階層式之可程式規劃陣列表現出較佳的臨界路徑延遲。混合式之可程式規劃陣列上的臨界路徑所行經的交換開關數目將比階層式之可程式規劃陣列多了兩倍左右。
同時，我們也將就可編程邏輯陣列之輸入以及乘積的大小，研究實作數據通路電路時所需要的面積以及消耗的延遲之間的關係。根據我們的實驗結果，三個輸入以及兩個乘積的可編程邏輯陣列將產生最小的面積，而四個輸入以及兩個乘積的可編程邏輯陣列將可得到最佳的延遲結果。當我們將可編程邏輯陣列產生的面積以及延遲結果和搜尋列表所產生的結果比較時，我們發現無論是面積或是延遲，可編程邏輯陣列都比搜尋列表更適合於實作數據通路電路。

We will study the area and delay comparisons for hierarchical and mixed FPGA structure.
In area evaluation, we shows that mixed FPGA is only 0.08\% smaller than hierarchical FPGA.
In delay evaluation, hierarchical FPGA has a better critical path delay.
The critical path of mixed FPGA passes through nearly 2 times more switch number than that of hierarchical FPGA.

We also study the PLA cell granularity for area and delay for data path circuit implementation.
It shows that 3-input 2-product term PLA cell results in the smallest area,
and 4-input 2-product term PLA cell is the best choice in terms of delay.
As to the comparisons of PLA and LUT cell structure,
PLA cell leads to better results than LUT cell in both area and delay.

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