本論文在探討藉由製程整合最佳化與新穎技術的引用，繼續微縮奈米級非揮發性記憶體的可行性。異常穿隧氧化層增長已分析清楚並可因淺溝渠絕緣製程改良而得到較好的可靠度改善。因耦合能力降低而使閘極間介電層之功能受限，可用電漿氮化來強化，同時，也有評估氧化鋁做作為未來閘極間介電層材料。製程設計可緩和字元線的尺寸效應，並因低電阻而可得到高寫入速度。高深寬比的位元線接觸窗因為矽基底漏失而造成嚴重接觸窗漏電流，選擇性矽磊晶當作金屬矽化之犧牲層以降低接觸窗電流。結合製程改良與新技術應用，浮停閘快閃記憶體可延展至五十奈米以下。
首先，以高密度電漿方法做自我對準淺溝渠絕緣填入時有水氣產生，最後造成穿隧氧化層不正常再生長，並有可能導致穿隧氧化層惡化；最佳化淺溝渠絕緣整合技術提出來減緩水氣侵入穿隧氧化層。其次，對奈米記憶胞而言，控制閘與浮停閘之間的耦合能力隨尺寸微縮而逐漸降低，因此寫入與抹除速度將面臨嚴峻挑戰；電漿氮化閘極間介電層被提出來強化閘間之耦合能力與寫入抹除速度；此外，電漿氧化也被提出來解決資料保存問題。高介電材料當做未來閘極間介電層之評估，以二氧化矽-三氧化二鋁-二氧化矽疊堆薄膜取代傳統閘極間介電層材質，也被用來研究熱抵抗性，低漏電及電子捕獲特性。再者，為了矽化鎢之側邊突出與操作速度問題改善，降低矽化鎢之片電阻及製程整合之最佳化也有做深入探討。最後，選擇性矽磊晶成長技術用來評估降低位元線接觸窗漏電流並且無電阻之損失。
採用我們的研究結果，傳統浮停閘快閃記憶體結構俱有延展至五十奈米以下之能力。

The objective of this dissertation is to investigate the feasibility of continued scaling for nanoscale floating gate NAND flash memory by means of integration optimization and novel process application. The analysis of anomalous tunnel oxide re-growth has been clarified and has obtained good reliability from shallow trench isolation modification. The functionality of interpoly dielectric layer constrained by coupling ratio reduction is enhanced using plasma nitridation method; simultaneously, aluminum oxide is evaluated as candidate for future interpoly dielectric material. The size effect of word line is mitigated by using process flow design, and then the low sheet resistance is proposed for achieving fast programming speed. The bit line contact with high aspect ratio structure suffered from severe junction leakage owing to silicon substrate loss; a novel selective epitaxial silicon growth technology is proposed as salicide sacrifice layer for junction leakage current reduction. To incorporate our process modification with novel technologies, the floating gate NAND can be easily extend to sub- 50 nm generation.
First of all, the advanced high-density plasma (HDP) method for self-aligned shallow trench isolation (SA-STI) suffers from existed moisture during trench gap filling, and then induces abnormal tunneling oxide re-growth; consequently, it probably exhibits poor tunnel oxide qualities. The optimal STI integrated process is proposed to mitigate moisture encroachment of tunnel oxide. Secondly, for nano-scaling dimension of memory cell, coupling capability between control gate and floating gate is gradually degraded, thus program / erase speed both face critical challenge; plasma nitridation of interpoly dielectric are proposed to enhance gate’s coupling and program / erase speed. Besides, solutions of retention problem by oxidation process of bottom oxide are provided. To evaluate higher dielectric constant material as future IPD candidate, SiO2-Al2O3-SiO2 (OAO) stacked film instead of conventional IPD material is studied for thermal resistance, lower current leakage and less electron trap. Thirdly, sheet resistance (Rs) reduction of WSix gate as well as integrated gate process optimization is explored in detail for WSix extrusion investigation and operation speed improvement. Consequently, the selective epitaxial growth silicon (SEG) technique is evaluated to reduce junction leakage for bit line contact without sacrificing contact resistance.
To adopt our studying results, the conventional floating fate NAND flash structure is capable of extending to 50 nm node and beyond.

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