新型非揮發性氮化層嵌入式邏輯記憶體之研究

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研究生：	賴漢昭 Lai, Han-Chao
論文名稱：	新型非揮發性氮化層嵌入式邏輯記憶體之研究 A New Nonvolatile Memory with Self-Aligned Nitride (SAN) Storage in Fully CMOS Compatible Logic Process
指導教授：	林崇榮 Lin, Chrong-Jung 金雅琴 King, Ya-Chin
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	146
中文關鍵詞：	邏輯非揮發性記憶體、氮化層、嵌入式、單次寫入式、單包兩位元
外文關鍵詞：	Self-Aligned Nitride, OTP, 2-Bits/Cell, SSI, Nitride Storage Node, Logic NVM
相關次數：	點閱：1 下載：0
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A novel One Time Programming (OTP) cell with nitride-based storage node has been proposed for logic nonvolatile memory applications without any additional masks or process steps for pure CMOS logic process. The fully-logic-compatible cell has been successfully demonstrated in 45nm-node technology with a cell size of 0.064um2, which achieves the smallest cell size, especially with 2- bits per cell characteristics. This cell adapting source side injection programming scheme has a wide on/off window and a superior writing efficiency. Highly reliable data retention characteristics also have been demonstrated in nitride storage node. Since the storage mechanism decouples from logic transistor gate oxide thickness, the scalability of the new cell is very promising along with advanced CMOS technology with high feasibility and solution for embedded NVM in advance logic circuits.

Abstract                             i
Acknowledgments                    ii
Contents                        iii
Figure Captions                    vi
Table Captions                    x

Chapter 1  Introduction                1
1-1.Introduction                    1
1-2. Typical properties of logic nonvolatile memory    4
1-2-1. Basic Operation Principle            4
1-2-2. Basic Programming Mechanisms            4
1-2-2-1. Channel Hot-Electron (CHE) Injection             5
1-2-2-2. Channel Initiated Secondary Electron (CHISEL) injection                                                  6
1-2-2-3. Band-to-Band Tunneling Induced Hot-Hole (BBHH) Injection                                                  7
1-2-2-4. Fowler-Nordheim Tunneling                      8
1-2-2-5. Source-Side Injection                      9
1-3. Goal and Organization of Dissertation             12

Chapter 2  Logic-Compatible Nonvolatile Memory    20
2-1. Introduction                                        20
2-2. Technology Benchmark of Logic-Compatible NVM    22
2-2-1. PMOS CHE: NeoFlash (Single Poly EPROM)             22
2-2-2. Oxide Breakdown: 3-Dimentional OTP             23
2-2-3. Oxide Breakdown: XPM                               24
2-2-4. Electro-Migration: Electrical Fuse             26
2-3. Summary                                        28

Chapter 3  Operation Mechanisms of SAN Cell             34
3-1. SAN Cell Structure                               35
3-1-1. TEM images of SAN Cell                      35
3-2. Key Process Steps for SAN Cell                      37
3-2-1. Gate Spacing Design                               39
3-3. Cell Operation Principles                      41
3-3-1. Programming Mechanism                      41
3-3-2. Hot Carrier Injection Point, Xc             43
3-3-3. Simulations of Program Operation             44
3-3-3-1. Electric Field Distribution                      44
3-3-3-2. Hot Carrier Generation Rate                      45
3-3-4. Read Operation                               46
3-3-4-1. Verification of trapped electrons location    48
3-3-5. Equivalent-circuit Verification             51
3-4. Program Characterization                      55
3-4-1. Polysilicon Gate Spacing Effect             55
3-4-2. PG Voltage Optimization                      57
3-4-3. SL Voltage Optimization                      58
3-4-4. Programming Efficiency                      59
3-5. Read Characterization                               61
3-5-1.Read Voltage Optimization                      61
3-6. UV Erase                                        63
3-7. NOR-Type Array                               65
3-8. Reliability                                        67
3-8-1. Data retention                               67
3-8-2. Program disturbance                               68
3-8-3. Read disturbance                               69
3-9. Summary                                        70

Chapter 4  Two Bits/Cell with 45 nm Logic Technology    89
4-1. 45nm Cell Structure and Layout                      89
4-2. Programming Operations for 2 Bits/Cell             91
4-2-1. Programming Time and PG Voltage Effects    92
4-2-2. Programming Optimization                      93
4-2-3. SG Voltage Effect                               95
4-2-4. Polysilicon Gate Space Effect                      96
4-2-5. Programming Flow of 2 Bits/Cell             97
4-3. Read Operation of 2 Bits/Cell                      99
4-3-1. I-V Curves of Read_L and Read_R             99
4-3-2. Read Operation Flow                               101
4-3-3. Read Voltage Optimization                      102
4-4. Erase Characteristics                               104
4-5. Reliability Characteristics                      105
4-5-1. Array Programming                               105
4-5-2. Program Disturbance                               105
4-5-3. Read Disturb                               106
4-6. Summary                                        108

Chapter 5  SAN Memory Shrinkage and Discussions       122
5-1. Introduction                                        122
5-2. Design and Structure Comparison                      124
5-3. Operations Characteristics Comparison             126
5-4. Operation Windows Comparison                      127
5-5. Summary                                        129

Chapter 6  Conclusion                               136
6-1. Summary                                        136
6-2. Recommendation for Future Work                      138

References                                        140

Publication List                                        145

                                

[1.1] Stan Augarten, “ State of the Art, ” Published by Ticknor & Fields, New Haven and New York, 1983
[1.2] D. Kahng and S. M. Sze, "A floating gate and its application to memory devices," Bell Syst. Tech. J., vol. 46, p. 1288, 1967.
[1.3] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash Memory Cells-An Overview,” Proc. IEEE, vol. 85, no. 8, pp. 1248-1271, 1997.
[1.4] S. Tam, P. Ko, and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET's,” IEEE Trans. Electron Dev., vol. ED-31, Sept. 1984, p. 1116-1125.
[1.5] T. H. Ning, C. M. Osburn, and H. N. Yu, “Emission probability of hot electrons from silicon into silicon dioxide,” J. Appl. Phys., Vol. 48, pp. 286-293, 1977.
[1.6] Y. Nakagume, E. Takeda, H. Kume, and S. Asai, “New observation of hot-carrier injection phenomena,” Jpn. J. Appl.Phys., vol. 22, p. 99, 1982.
[1.7] S. Mahapatra, S. Shukuri, and J. Bude, “CHISEL Flash EEPROM-Part I : Performanceand Scaling,” IEEE Trans. Electron Dev., vol. 49, no. 7, pp. 1296-1301, 2002.
[1.8] D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, “The scaling properties of CHISEL and CHE injection efficiency in MOSFETs and flash memory cells,” in Tech. Dig. Int’l Electron Dev. Meet., 1999, p. 275-278
[1.9] J. D. Bude et al, “Secondary electron flash-A high performance low power flash technology for 0.35 μm and below,” in Tech. Dig. Int’l Electron Dev. Meet., 1997, p. 279-282
[1.10] Y. Taur and T. H. Ning, “ Fundamentals of Modern VLSI Devices, ” Published by CambridgeUniv. Press, New York, 1998
[1.11] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2,” J. Appl. Phys., Vol. 40, No. 1, pp. 278-283, Jan. 1969
[1.12] Van Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken, and H. E. Maes, “HIMOS—a high efficiency Flash EEPROM cell for embedded memory applications,” IEEE Trans. Elect. Dev., vol. ED-40, p. 2255, 1993.
[1.13] R. Hoffmann, C. Werner, W. Weber, and G. Dorda, "Hot-electron and hole emission effects in short n-channel MOSFET's," IEEE Trans. Elect. Dev., vol. ED-32, p. 691, 1985.
[1.14] J. Van Houdt, P. Heremans, L. Deferm, G. Groeseneken, and H. E. Maes, "Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications," IEEE Trans. Elect. Dev., vol. ED-39, p. 1150, 1992.
[1.15] A. Wu, T. Chan, P. Ko, and C. Hu, "A novel high-speed, 5-V programming EPROM structure with source-side injection," IEEE IEDM Tech. Dig., p. 584, 1986.
[2.1] Ching-Sung Yang, Shih-Jye Shen ,and Ching-Hsiang Hsu ,"Single Poly UV-Erasable Programmable Read Only Memory, "US Patent # US 6,882,574 B2,Apr.19,2005.”
[2.2] Robert S.C. Wang, Rick S.J. Shen, Charles C.H. Hsu,” Neobit-high reliable Logic Non-Volatile Memory (NVM),” IPFA, 2004, pp. 111 – 114.
[2.3] F. Li, X. Yang, A. T. Meeks, J.T. Shearer, and K.Y. Le “Evaluation of SiO2 antifuse in a 3D-OTP memory, ”IEEE Device and Material Reliability, vol.4, pp. 416-421, Sept. 2004.
[2.4] S. B. Herner, ”Vertical p–i–n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM,” IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004.
[2.5] T J. Peng, G .Rosendale , M . Fliesler , D. Fong , J. Wang ,C. Ng ,Zs Liu ,Harry Luan," A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology", IEEE 2006.
[2.6] Peng, Jack et al., “ Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultrathin dielectric,” US Patent# US6,671,040 B2, Dec.30,2003.
[2.7] Johannes Fellner, “A one time programming cell using more than two resistance levels of a PolyFuse. ”IEEE Custom Integrate Circuit, pp.263-266, Sept. 2005.
[3.1] Han-Chao Lai, Kai-Yuan Cheng, Ya-Chin King, and Chrong-Jung Lin,” A 0.26-um2 U-shape Nitride Based Programming Cell on Pure 90nm CMOS Technology, ” IEEE Electron Device Lett., Vol. 28, pp. 837-839, Sept. 2007
[3.2] Han-Chao Lai, Chia-En Huang, Ya-Chin King, and Chrong-Jung Lin,” Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal–Oxide–Semiconductor Logic Technology,”, JJAP, pp. 8369-8374, 2008.
[3.3] Johannes Fellner, “A One Time Programming Cell Using More than Two Resistance Levels of a PolyFuse. ”IEEE Custom Integrate Circuit, pp.263-266, Sept. 2005
[3.4] Hiroshi Ito, Toshimasa Namekawa,” Pure CMOS One-time Programmable Memory Using Gate-Ox Anti-fuse, ”IEEE Custom Integrate Circuits Conference, 2004, pp.469 – 472, Oct. 2004
[3.5] Robert S.C. Wang, Rick S.J. Shen, Charles C.H. Hsu,” Neobit□ -High Reliable Logic Non-Volatile Memory (NVM),” IPFA, 2004, pp. 111 – 114.
[3.6] A. Wu, T. Chan, P. Ko, and C. Hu, "A novel high-speed, 5-V programming EPROM structure with source-side injection," IEEE IEDM Tech. Dig., p. 584, 1986.
[3.7] Van Houdt, L. Haspeslagh, D. Wellekens, L. Deferm, G. Groeseneken, and H. E. Maes, “HIMOS—a high efficiency Flash EEPROM cell for embedded memory applications,” IEEE Trans. Elect. Dev., vol. ED-40, p. 2255, 1993.
[5.1] B.Yu, “15nm Gate Length Planar CMOS Transistor”, pp.937-939, IEDM, 2001.
[5.2] S.Pan, “Nonvolatile Memory Challenges toward Gigabit and Nano-scale Era and a Nano-scale Flash Cell: PHINES”, Extended abstracts of the 2002 International Conference on Solid State Devices and Materials, pp.152-153, 2002.

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