研究生: |
李奕萱 Lee, Yi-Hsuan |
---|---|
論文名稱: |
以變換電壓之下的抖動量測量為基礎的鎖相迴路嚴格測試方法 Rigorous Test Flow for PLL using Jitter Measurement with VDD Sweeping |
指導教授: |
黃錫瑜
Huang, Shi-Yu |
口試委員: |
吳誠文
Wu, Cheng-Wen 李昆忠 Lee, Kuen-Jong 黃俊郎 Huang, Jiun-Lang 洪浩喬 Hong, Hao-Chiao |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2021 |
畢業學年度: | 109 |
語文別: | 中文 |
論文頁數: | 41 |
中文關鍵詞: | 抖動 、峰對峰值抖動量 、嚴密的測試流程 、基於抖動的校準 、極大極小時間數位轉換器 、弱裝置 |
外文關鍵詞: | jitter, pea-to-peak jitter amount, rigorous test flow, dithering-based calibration, min-Max Time-to-Digital Converter, weak device |
相關次數: | 點閱:2 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
輸出時脈週期的變化(稱為抖動)通常是鎖相迴路的重要指標。在本論文中,我們提出「抖動測量方法」和「嚴密的測試流程」來檢查鎖相迴路在各種情況下都有一定的可靠性。「抖動測量方法」主要的功能為 — 基於抖動的校準。使用極大極小時間數位轉換器 (min-MAX Time-to-Digital),我們可以即時記錄最小周期代碼和最大周期代碼,最小周期代碼和最大周期代碼的差值表示峰對峰值抖動量代碼,通過提出的基於抖動的校準,我們可以進一步將平均峰對峰值抖動量代碼映射到其相應的絕對峰對峰值抖動量,單位為皮秒。
下一步是達成目標:識別在惡劣操作環境下可能發生故障的脆弱裝置。我們提出「嚴密的測試流程」可以測量在模擬惡劣操作環境下其鎖相迴路的性能。其獨特的功能 — 透過抖動測量方法進而得到溫度對應電壓之映射方法。在測試流程結束時,將峰對峰值抖動量作為「穩健性指標」來篩選是否為脆弱裝置。
我們在90nm CMOS製程上實施基於鎖相迴路提出的測試流程,「抖動測量方法」的後仿真模擬顯示:我們不僅可以檢測到傳統基於採樣的方法無法得到的短時瞬態誤差,而且還可以得到準確的絕對峰對峰值抖動量,以達成在線抖動驗證的目的;無法通過簡單的傳統測試來辨別脆弱裝置的疑慮可以透過我們提出「嚴密的測試流程」來解決。
Regarding a Phase-Locked Loop (PLL), the change of its output clock period known as jitter is often an important metric. In this thesis, we propose a “jitter measurement scheme” and “rigorous test flow” to check the robustness of a PLL. Our “jitter measurement scheme” has a unique feature – A Dithering-Based Calibration. With the min-MAX Time-to-Digital Converter (called min-MAX TDC), we be able to derive both the minimum period code and the maximum period code recorded in a monitoring session on the fly, and their difference denotes a Peak-to-Peak Jitter Amount (PPJA) code. With the proposed Dithering-Based Calibration, we can further map the average PPJA code (avg-p-code) into its corresponding absolute PPJA in picoseconds.
The further goal is to identify weak devices that could fail under hostile operating conditions. We devise a “rigorous test flow” to measure the performance of a PLL device with “mimicked” hostile operating conditions. Its unique feature – A temperature-to-VDD-mapping scheme based on our jitter measurement scheme. At the end of the test, the peak-to-peak jitter is used as a “robustness indicator” to guide the screening process of weak devices.
We have implemented the proposed method for an in-house cell-based PLL using a 90nm CMOS process. The post-layout simulation of “jitter measurement scheme” demonstrates that we can not only detect some short-time transient errors that could have escaped a traditional sampling-based method, but also report an accurate absolute peak-to-peak jitter amount to serve the purpose of online jitter validation. The results of “rigorous test flow” obscure symptoms that might have escaped a simple traditional test can now be revealed.
[1] T. H. Kim, R. Persaud, and Chris H. Kim. "Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, pp. 874-880, 2008.
[2] Y. Li, Y. M. Kim, E. Mintarno, D. S. Gardner, and S. Mitra, “Overcoming Early-Life Failure and Aging for Robust Systems,” IEEE Design & Test of Computers, Vol. 26, No. 6, pp. 28-39, 2009.
[3] C. Serafy and A. Srivastava, "Online TSV Health Monitoring and Built-In Self-Repair to Overcome Aging", Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 224-229, 2013.
[4] G.-H. Lian, W.-Y. Chen, and S.-Y. Huang, "Cloud-Based Online Ageing Monitoring for IoT Devices”, IEEE Access, Vol. 7, pp. 135954-135971, 2019.
[5] J. Carretero, X. Vera, P. Chaparro, and J. Abella, “Microarchitectural Online Testing for Failure Detection in Memory Order Buffer”, IEEE Trans. on Computers, Vol. 59, No. 5, pp. 623-637, 2010.
[6] S.-F. Yang, Z.-Y. Wen, S.-Y. Huang, K.-H. Tsai, and W.-T. Cheng, "Circuit and Methodology for Testing Small Delay Faults in the Clock Network", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 37, No. 10, pp. 2087-2097, 2018.
[7] S.-Y. Huang, M.-T. Tsai, H.-X. Li, Z.-F. Zeng, K.-H. (Hans) Tsai, and W-.T. Cheng, "Non-Intrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34, No 12, pp. 2039-2048, Dec. 2015.
[8] G.-H. Lian, S.-Y. Huang, and W.-Y. Chen, "Cloud-Based PVT Monitoring System for IoT Devices," Proc. of IEEE Asian Test Symp. (ATS), pp. 76-81, Nov. 2017.
[9] H. Shaheen, G. Boschi, G. Harutyunyan, and Y. Zorian, “Advanced ECC Solution for Automotive SoCs”, Proc. of IEEE Int’l Symp. on On-Line Testing and Robust System Design (IOLTS), pp. 71-73, 2017.
[10] F. Su and P. Goteti, “Improving Analog Functional Safety Using Data-Driven Anomaly Detection”, Proc. of IEEE Int’l Test Conf., Paper 13.3, pp. 1-10. 2018.
[11] S. Sunter and A. Roy, “On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz,” IEEE Design & Test of Computers, July-Aug., pp. 314-321, 2004.
[12] S. Sunter and A. Roy, “Purely Digital BIST for any PLL or DLL”, Proc. of IEEE European Test Symp., pp. 1-6, 2007.
[13] R. Kinger, S. Narasimhawsamy, and S. Sunter, “Experiences with Parametric BIST for Production Testing PLLs with Picosecond Precision”, Proc. of IEEE Int’l Test Conf., pp. 1-9, 2010.
[14] J.-J. Huang and J.-L. Huang, “An Infrastructure IP for On-Chip Clock Jitter Measurement”, IEEE Int’l Conf. on Computer Design, pp. 1-6, 2004.
[15] P.-Y. Chou and J.-S. Wang, “An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit with Automatic Resolution Calibration for high PVT-Variation Resilience”, IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 66, No. 7, pp. 2508-2518, July 2019.
[16] J. Yu and F. F. Dai, "On-Chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter," Proc. of Asian Test Symp., pp. 167-170, 2010.
[17] T. Hashimoto, H. Yamazaki, A. Muramatsu, T. Sato, and A. Inoue, “Time-to-Digital Converter with Vernier Delay Mismatch Compensation for High Resolution On-Die Clock Jitter Measurement,” Digest of the Int’l Symp. on VLSI Circuits, pp. 166-167, June 2008.
[18] W. Chu and S.-Y. Huang, “Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor”, IEEE Trans. on Emerging Topics in Computing, (Early Access Article), 2019.
[19] P. Chen, S.-I. Liu, and J.-S. Wu, “A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, Sep. 2000.
[20] Y. Liu, U. Vollenbruch, Y. Chen, C. Wicpalek, L. Maurer, Z. Boos, and R. Weigel, “Multi-stage Pulse Shrinking Time-to-Digital Converter for Time Interval Measurements,” in Proc. of European Microwave Integrated Circuit Conf. (EuMIC), pp. 267-270, 2007
[21] C.-C. Chen, S.-H. Lin, and C.-S. Hwang, “An Area-Efficient CMOS Time-to-Digital Converter Based on Pulse-Shrinking Scheme,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 61, no. 3, Mar. 2014.
[22] C.-H. Wu, S.-Y. Huang, M. Chern, Y.-F. Chou, and D.-M. Kwai, "A Resilient Cell-Based Architecture for Time-to-Digital Converter", Proc. of IEEE Int'l Symp. on VLSI, pp. 7-12, Bochum, Germany, pp. 7-12, July 2017.
[23] C.-H. Wu, S.-Y. Huang, Y.-F. Chou, and D.-M. Kwai, "Time-to-Digital Converter Compiler for On-Chip Instrumentation", IEEE Design and Test (D&T), Early Access Article, 2020.
[24] W.-H. Chen, C.-C. Hsu, and S.-Y. Huang, "Rapid PLL Monitoring By a Novel min-MAX Time-to-Digital Converter", Proc. of IEEE Int'l Test Conf., (ITC), pp. 1-8, 2020.
[25] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, March 2014.
[26] C.-E. Lee and S.-Y. Huang, "A Cell-Based Fractional-N Phase-Locked Loop Compiler," Proc. of IEEE Int'l Conf. on Synthesis, Modeling, Analysis, and Simulation Methods and Applications to Circuit Design (SMACD), pp. 273-276, (July 2018).