隨著超大型積體電路設計技術的快速發展，場可程式化邏輯陣列
(Field Programmable Gate Array, FPGA)晶片的應用也愈益廣泛。
而一個完整的FPGA 設計是極具挑戰性的，那包含了架構分析，自動
化軟體(CAD tools)的研發，電路設計，佈局(layout) ，電路模擬和
驗證。在這篇論文中，我們提出了一個針對新的階層式場可程式化邏
輯陣列(Hierarchical FPGA, HFPGA)架構的實體電路設計方法，藉由
適當的架構參數(parameters)選擇，加以自動化的金屬層(metal
layer)繞線機制，能夠有效的縮短此架構的FPGA 晶片的開發時間。
利用此方法我們實際設計了一個四個階層的HFPGA，電路模擬結果顯
示此電路達到我們預期的功能，另外我們更改進了一個Island Style
FPGA 繞線延遲內建自我測試(Built-In Self-Test, BIST)電路，使
其能夠適用於新的階層式架構並簡化其操作，電路模擬結果亦顯示此
自我測試電路可在此新架構中正確的工作。

Creating a new FPGA is a challenging task. Currently it takes approximately 50 to 200 person years from architecture exploration, CAD tools development, circuit design, layout to verification [1]. Our work focused on hardware implementation of the FPGA with a new developed hierarchical connection topology(HFPGA), since the development of the CAD tools for this connection topology
has been addressed in [2, 3]. We proposed a methodology to shorten the design time of the HFPGA by adopting the regularity we explored to automate the process of the complicated interconnection routing. A case of a four level HFPGA layout was constructed. Simulation result reveals the circuits implemented in the HFPGA functioned correctly. In addition, we modified and improved the interconnection delay BIST circuit [4] for our HFPGA. Simulation results indicated that the delay testing techniques can be applied to the HFPGA successfully.

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