本論文針對三維積體電路提出一個平台式的設計方法，此方法藉由製造上的重複使用來降低三維晶片的成本。我們設計的三維積體電路架構能使得一組應用的總成本最少。此架構包含一個能夠被各個應用重複使用的平台晶片層以及一個可以客製化的晶片層。共用的平台層已經包含許多功能，因此客製化的晶片層只要針對個別應用加上缺乏的功能再堆疊到平台上即可。平台層被多個應用共用，因此能藉由很大的產量來稀釋成本。
為了評估平台層各種組態對成本的影響，本論文發展出一個三維積體電路的成本模型以及一個平台層的產生器。平台產生器使用模擬退火法來找出能夠讓各個應用總成本最低的平台。
實驗結果顯示，此平台式設計方法確實能有效地降低三維積體電路成本，而平台產生器也能找到接近最佳解的平台。

We propose a platform-based approach for 3D IC implementation of complex electronics systems. We emphasize Manufacturing Reuse to lower the overall cost of implementing and mass-producing 3D chips for multiple applications. Given a set of applications, each employs a set of IPs and needs a certain amount of mass-production volume, our objective is to design a 3D IC architecture such that the total design-plus-manufacture cost is minimized for all applications. We achieve this by defining certain platform-dies that can be prefabricated-and-reused across multiple applications. Our target 3D IC stack consists of platform dies and customized dies. Platform dies can be manufactured in huge volume at very low unit cost and used in many applications. Customized dies for individual application, on the other hand, will be smaller and easier to implement, as most functionality has been allocated to the platform dies. We have developed a 3D IC cost model for our platform generator to evaluate platform-layer configurations. Based on simulated-annealing optimization, this generator finds a platform that minimizes the overall cost of a set of applications. Experimental results indicate that Chipsburger is cost-effective for a wide range of volume requirements.

[1]K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,” Proceedings of the IEEE, vol. 89, no. 5, pp. 602–633, May 2001.
[2]R. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1214–1224, 2006.
[3]D. Ragan, P. Sandborn, and P. Stoaks, “A detailed cost model for concurrent use with hardware/software co-design,” in Proceeding of Design Automation Conference, pp. 269–274, June 2002.
[4]P. Mercier, S. Singh, K. Iniewski, B. Moore, and P. O’Shea, “Yield and cost modeling for 3D chip stack technologies,” in Proceeding of Custom Integrated Circuits Conference, pp. 357–360, September 2006.
[5]C. Liu, J.-H. Chen, R. Manohar, and S. Tiwari, “Mapping system-on-chip designs from 2-D to 3-D ICs,” in Proceeding of IEEE International Symposium on Circuits and Systems, vol. 3, pp. 2939–2942, May 2005.
[6]R.Weerasekera, L.-R. Zheng, D. Pamunuwa, and H. Tenhunen, “Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs,” in Proceeding of IEEE/ACM International Conference on Computer-Aided Design, pp. 212–219, November 2007.
[7]X. Dong and Y. Xie. “System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs),” in Proceeding of Asia and South Pacific Design Automation Conference, pp. 234–241, January 2009.
[8]J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits – a design perspective, 2nd Ed., Upper Saddle River, NJ: Prentice Hall, 2003.
[9]A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM Journal of Research and Development, vol. 50, no. 4, pp. 491–506, July 2006
[10]B. T. Murphy, “Cost-size optima of monolithic integrated circuits,” Proceedings of the IEEE, vol. 52, pp. 1537–1545, December 1964.
[11]A. Salam, N. F. Bhuiyan, G. J. Gouw, S. A. Raza, “Estimating design effort in product development: a case study at Pratt & Whitney Canada,” in Proceeding of IEEE International Conference on Industrial Engineering and Engineering Management, pp. 989-993, December 2007.
[12]A. Chang, “Case study of a 65-nm SoC design,” IEEE Design and Test Computer. vol 26, no.2, pp. 14–19, March-April 2009.
[13]S. Kirkpatrick, C. D. Gelatt Jr., and M. P. Vecchi, “Optimization by simulated annealing,” Science, vol. 220, no. 4598, pp. 671–680, May 1983.