低溫複晶矽薄膜電晶體已成為實現高畫質可攜式平面顯示器的關鍵技術。其另一項具革命的技術發展，為系統面板(System on Panel: SOP)的實現；既是將所有的周邊電路，關鍵元件，驅動電路等，全部整合於玻璃基板上。電晶體尺寸的微縮可以加快電路運作的速度，提高積體電路元件的密度，增加晶片的功能及設計彈性。因此依據金氧半電晶體微縮法則(Scaling rule)，將複晶矽薄膜電晶體尺寸微縮化，會得到相同的效能提升，如此方可將周邊電路，關鍵元件，驅動電路等，全部整合於玻璃基板上，來實現系統面板的目標。然而複晶矽薄膜電晶體仍具有功率大量消耗的問題，故解決功率大量消耗的課題是值得探討的。由於非揮發性記憶體可在低功率消耗的狀態下操作，為了達到系統面板的需求，本論文成功的結合複晶矽薄膜電晶體的新穎製程和非揮發性記憶體的特性，製作出高效能的非揮發性薄膜電晶體。研究結果發現，具三面閘極與奈米線以氮化矽為儲存單元的矽-氧化矽-氮化矽-氧化矽-複晶矽 (SONOS) 非揮發性複晶矽薄膜記憶體用有很好的可靠度，如較
好的資料保存能力（Retention）和較好的重複讀寫的忍受度（Endurance），並且可達到二位元（Two-bit）操作。對於系統面板的整合，與三維立體堆疊式元件上，極具產業運用價值。
在論文的第一部分，我們提出具三面閘極的奈米線的矽-氧化矽-氮化矽-氧化矽-複晶矽(SONOS)非揮發性複晶矽薄膜記憶體的結構來改善一般傳統的複晶矽薄膜電晶體(TFT)的特性。實驗結果指出，由於三向閘極及額外的轉角電流貢獻，使奈米線結構SONOS非揮發性複晶矽薄膜記憶體具有較佳之電性特性。此外，具有十條奈米線通道的SONOS非揮發性複晶矽薄膜記憶體較其他的薄膜電晶體(如單通道或五條奈米線通道的非揮發性複晶矽薄膜記憶體)有著更好的電性，主要是由於較多的轉角數目及其轉角效應所引起的閘極邊側散發的邊際電場造成的較大的電場，使得元件具有更好的閘極控制能力。因此，具奈米線結構之SONOS非揮發性複晶矽薄膜記憶體的元件特性主要的改善來自於電力線聚集所產生的高電場效應。在此，所提出之奈米線SONOS揮發性複晶矽薄膜記憶體因具有較好之閘極控制能力，所以有較快的寫入/抹除效率，此外，這樣的元件也具有良好之耐操度與資料保存特性。
在論文的第二部分，我們將探討具奈米線結構之SONOS非揮發性複晶矽薄膜記憶體的二位元效應。由於氮化矽為局部離散的電子捕陷機制，在適當的操作條件下，可在一個單元內儲存兩個位元。在此研究我們採用通道熱電子 (Channel Hot Electron：CHE) 的寫入機制和通道熱電洞注入 (Hot Hole Injection：HHI) 的抹除機制，研究結果顯示出兩位元的寫入與抹除並不會互相影響，證實非揮發性記憶體可以兩個位元操作。

Chapter 1
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