幀內預測是H.264/AVC影像編碼標準中幀內編碼方式的第一個程序，而幀內編碼方式是利用移除空間多餘的資訊達到影像壓縮的目的。為了支援高畫質影像編碼的應用，我們提出了一個高平行架構的幀內預測器以加快總預測時間。經過系統需求分析後，幀內預測器的效能必須達到每個時鐘脈衝週期產生32個luma 4x4預測畫素或者16個luma 16x16、chroma 8x8的預測畫素。此外，我們提出一個可半重新裝配的硬體架構、一個處理單元的最佳化方法以及一個預測模式層級的排程方案，去達到降低硬體需求。我們使用verilog 硬體描述語言實作所提出的硬體架構。在200MHz 的運作時脈下，所需之邏輯閘數為20.4K。與直接實作的結果做比較，所提出的硬體架構可以減少90.2%的硬體面積。此外，所提出預測器在產生預測畫素需要4時鐘脈衝週期以完成一個luma 4x4模式的預測，花費3.5K個邏輯閘；而需要96個時鐘脈衝週期以完成luma 16x16、chroma 8x8模式的預測，花費11.7K個邏輯閘。最後，所提出的幀內預測器已經成功的整合進入H.264/AVC幀內編碼器，其效能可以在運作在138MHz達到即時編碼1080p全高畫質之影像。

Intra Prediction is the first process of H.264/AVC intra encoding, which compresses video by removing spatial redundancy. For high-resolution applications, we propose a highly parallel architecture of Intra Prediction Generation Engine (IPGE) to shorten the prediction time. An analysis derives that the required degree of Pixel-Level Parallelism (PLP) for luma 4x4 is 32 pixel/cycle, whereas for luma 16x16 and chroma 8x8 is 16 pixel/cycle. In addition, we propose a semi-reconfigurable architecture, a Processing Element Optimization Method (PEOM), and a Mode-Level Scheduling Scheme (MLSS) to reduce hardware usage. The proposed design has been implemented in Verilog RTL and synthesized targeted towards a TSMC 0.13μm CMOS cell library. Its gate count is 20.4K when running at 200MHz. In comparison with direct implementation, the proposed architecture reduces 90.2% of gate count. The engine for all luma 4x4 modes consumes 3.5K gates and takes 4 cycles to predict a 4x4 block; the engine for luma 16x16/chroma 8x8 modes consumes 11.7K gates and takes totally 96 cycles to generate a 16x16 macroblock. We have integrated the proposed design into an H.264/AVC intra encoder which can process 30fps 1080p HD video when running at 138MHz.

Bibliography

[1] “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC),” JVT-G050, 2003.
[2] Information Technology-Coding of Audio-Visual Objects-Part2: Visual, 1999
[3] Video Coding for Low Bit Rate Communication, 1998.
[4] Information Technology-Generic Coding Moving Pictures and Associated Audio
Information: Video, 1996.
[5] A. John, F. Kossentini, H. Schwarz, T. Wiegand and G. J. Sullivan, “Performance Comparison of Video Coding Standards using Lagrangian Coder Control,” Proceedings of International Conference on Image Processing, vol. 2, pp. 501-504, September 2002.
[6] A. Al, B. P. Rao, S. S. Kudva, S. Babu, D. Suman and A. V. Rao, “Quality and Complexity Comparison of H.264 Intra Mode with JPEG2000 and JPEG,” International Conference on Image Processing, vol. 1, pp. 525-528, October 2004.
[7] T. C. Chen, H. C. Fang, C. J. Lian, C. H. Tsai, Y. W. Huang, T. W. Chen, C. Y. Chen, Y. H. Chen, C. Y. Tsai and L. G. Chen, “Algorithm Analysis and Architecture Design for HDTV Applications - a look at the H.264/AVC video compressor system.” IEEE Circuits and Devices Magazine, vol. 22(3), pp. 22 - 31, May-June 2006.
[8] T. Wiegand, G. J. Sullivan, G. Bjntegaard and A. Luthra, “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13(7), pp. 560-576, July 2003.
[9] D. Marpe, T. Wiegand and G. J. Sullivan, “The H.264/MPEG4 Advanced Video Coding Standard and its Applications,” IEEE Communications Magazine, vol. 44(8), pp.134-143, August 2006
[10] JVT H.264/AVC Reference Software JM11.0
[11] Y. W. Huang, B. Y. Hsieh, T. C. Chen and L. G. Chen, “Analysis, Fast Algorithm, and VLSI Architecture Design for H.264/AVC Intra Frame Coder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15(3), pp. 378-401, March 2005.
[12] C. W. Ku, C. C. Cheng, G. S. Yu, M. C. Tsai and T. S. Chang, “A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 16(8), pp. 917-928, August 2006.
[13] D. W. Li, C. W. Ku, C, C. Cheng, Y. K. Lin and T. S. Chang, “A 61MHz 72K Gates 1280x720 30FPS H.264 Intra Encoder,” IEEE International Conference on Acoustics, Speech and Signal Processing, vol. 2, pp. (II) 801-804, April 2007.
[14] K. Suh, S. Park and H. Cho, “An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder,” Electronics and Telecommunications Research Institute Journal, vol. 27(5), pp. 511-524, October 2005.
[15] C. C. Cheng, C. W. Ku and T. S. Chang, “A 1280/spl times/720 pixels 30 Frames/s H.264/MPEG-4 AVC Intra Encoder,” IEEE International Symposium on Circuits and Systems, pp. 5335-5338, May 2006.
[16] C. H. Tsai, Y. W. Huang and L. G. Chen, “Algorithm and Architecture Optimization for Full-mode Encoding of H.264/AVC Intra Prediction,” Midwest Symposium on Circuits and Systems, vol. 1, pp. 47-50, August 2005.
[17] Y. C. Kao, H. C. Kuo, Y. T. Lin, C. W. Hou, Y. H. Li, H. T. Huang and Y. L. Lin, “A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding,” IEEE Asia Pacific Conference on Circuits and Systems, pp. 562-565, December 2006.
[18] C. C. Cheng and T. S. Chang, “Fast Three Step Intra Prediction Algorithm for 4/spl times/4 Blocks in H.264,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1509-1512, May 2005.
[19] G. Jin, J. S. Jung and H. J. Lee, “An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing,” IEEE International Symposium on Circuits and Systems, pp. 1605-1608, May 2007.
[20] B. Meng and O. C. Au, “Fast Intra-prediction Mode Selection for 4A Blocks in H.264,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 3, pp. (III) 389-92, April 2003.
[21] J. C. Wang, J. F. Wang, J. F. Yang and J. T. Chen, “A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra-Prediction,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 17(10), pp. 1414-1422, October 2007.
[22] IEEE standard for Verilog Hardware Description Language 2001, IEEE Std. 1394-2001. Piscataway, NJ: Institute of Electrical and Electronics Engineers, 2001