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研究生: 謝昇融
論文名稱: 考慮總成本最小化下建構半導體製造需求滿足模型及其實證研究
Construct a Demand Fulfillment Model Considering Minimizing Total Cost : An Empirical Study in Semiconductor Manufacturing
指導教授: 簡禎富
口試委員: 簡禎富
林國勝
吳吉政
學位類別: 碩士
Master
系所名稱: 工學院 - 工業工程與工程管理學系
Department of Industrial Engineering and Engineering Management
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 102
中文關鍵詞: 需求滿足半導體製造光罩配置新產品投片分配產能利用跨廠支援
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  • 半導體製造業所投入的設備成本昂貴,使得產能充分的利用為晶圓廠面臨需求所決策之問題。並且晶圓代工是以顧客導向為主,因此客戶需求滿足(Demand Fulfillment)為其企業之經營目標。因為半導體製程相當複雜,產品必須先經過光罩製作、試產及驗證等流程後才可進行量產,並且機台種類的不同使得光罩圖型將根據其所需要的機台才可進行製造而產生光罩配置之問題。
    由於新產品的需求具有不確定性,對公司產能運用造成困難,而在新產品投片分配的過程中,將決定新產品投入的晶圓廠,並且必須考慮前置時間後才可進行生產,因此本研究將探討新產品投片對需求滿足之影響。
    本研究考慮半導體製造業需求與限制,進行新產品與現有產品投片的分配,並以成本最小化為目標建立需求滿足模型,以提升半導體製造業廠商的競爭力。最終以半導體製造業為實證對象,進行分析案例公司與模型分配結果,並提出兩者間差異處。


    目錄 I 圖目錄 II 表目錄 III 第一章 緒論 1 1.1研究背景 1 1.2研究動機與重要性 3 1.3研究目的 4 1.4論文結構 5 第二章 理論基礎 6 2.1產品標準成本規劃 7 2.2微影作業區域訂單分配 26 2.3實際成本結算 31 2.4產能分配 44 第三章 研究架構 47 專業術語與符號 49 3.1問題定義 52 3.2界定利基 54 3.3微影區域需求滿足模式建構 55 3.4客觀敘述與感受 63 3.5綜合判斷與決策 63 第四章 實證研究 64 4.1案例公司背景與問題定義 64 4.2界定利基 67 4.3架構影響關係 68 4.4客觀敘述與感受 69 4.5綜合判斷與決策 70 第五章 結論 97 參考文獻 99

    簡禎富(2005),決策分析與管理,雙葉書廊,台北。
    簡禎富、施義成、林振銘、陳瑞坤(2005),半導體製造技術與管理,清華大學出版社,新竹。
    Chen, J. C. and Chen, C. W., (2010), “Capacity Planning of Serial and Batch Machines with Capability Constraints for Wafer Fabrication Plants,” International Journal of Production Research, Vol. 48, No. 11, pp. 3201-3223.
    Chien, C. F., Wu, J. Z., and Wu, C. C., (2011) “A two-stage stochastic programming approach for new tape-out allocation decisions for demand fulfillment planning in semiconductor manufacturing,” Flexible Services and Manufacturing Journal, (Online First, DOI:10.1007/s10696-011-9109-0).
    Chien, C. F., Chen, Y. J., and Peng, J. T., (2010) “Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product life cycle,” International Journal of Production Economics, Vol. 128, No. 2, pp. 496-509.
    Chien, C. F., Hsu, C. Y., Chou, H. S., and Lin, C. W., (2006) “Overall Wafer Effectiveness (OWE): A Novel Industry Standard for Wafer Productivity,” Proceedings of International Symposium on Semiconductor Manufacturing 2006, 25-27 September, Tokyo, Japan, pp. 317-320.
    Chou, Y. C. and Hong, L. H., (2000), “A methodology for product mix planning in semiconductor foundry manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 278–285.
    Chou, Y. C., Cheng , C. T., Yang, F. C., and Liang,Y. Y., (2007), “Evaluating alternative capacity strategies in semiconductor manufacturing under uncertain demand and price scenarios,” International Journal of Production Economics, Vol. 105, No. 2, pp. 591–606.
    Chung, S. H., Huang, C. Y., and Lee, A. H. I., (2006), “Capacity allocation model for photolithography workstation with the constraints of process window and machine dedication,” Production Planning & Control, Vol. 17, No. 7, pp. 678-688.
    Cooper, R. and Kaplan, R. S., (1992), “Activity-Based systems: measuring the costs of resource usage,” Accounting Horizons, September, pp 1-14
    Erkoc, M. and Wu, S. D., (2005), “Managing High-Tech Capacity Expansion via Reservation Contracts,” Production and Operations Management, Vol. 14, No. 2, pp. 232-251.
    Geng, N. and Jiang, Z., (2010), “A review on strategic capacity planning for the semiconductor manufacturing industry,” International Journal of Production Research, Vol. 47, No. 13, pp. 3639-3655.
    Kim, S., Yea, S. H., and Kim, B., (2002), “Shift scheduling for steppers in the semiconductor wafer fabrication process,” IIE Transactions, Vol. 34, No. 2, pp. 167-177.
    Klemmt, A., Lange, J., Weigert, G., Lehmann, F., and Seyfert, J., (2010), “A multistage mathematical programming based scheduling approach for the photolithography area in semiconductor manufacturing,” Proceedings of the 2010 Winter Simulation Conference (WSC), pp. 2474-2485
    Miwa, T., Nishihara, N., and Yamamoto, K., (2005), “Automated stepper load balance allocation system,” IEEE Transactions on semiconductor manufacturing, Vol. 18, No. 4, pp. 510-516.
    Moore, G. E., (1998), “Cramming more components onto integrated circuits,” Proceedings of the IEEE, Vol. 86, No. 1, pp. 82-85.
    Mouli, C. and Winstead, C. H., (2007), “Tapeout Execution System (TES), a key enabler of DFM/Co-optimization,” Proceedings of International Symposium on Semiconductor Manufacturing 2007, 15-17 October, Santa Clara, California, pp. 1-4.
    Pham, H. N. A., Shr, A. and Chen, P. P., (2008), “An integer linear programming approach for dedicated machine constraint,” Seventh IEEE/ACIS International Conference on Computer and Information Science, Portland, Oregon, pp. 69-74.
    Rupp, T. M. and Ristic, M., (2000), “Fine planning for supply chains in semiconductor manufacture,” Journal of Materials Processing Technology, Vol. 107, No. 1, pp. 390-397.
    Shih, W., Chien, C. F., Shih, C. T., Chang, J., (2009), “The TSMC Way: Meeting Customer Needs at Taiwan Semiconductor Manufacturing Co.,” Harvard Business School Case610-003(2009).
    Toktay, L. B. and Uzsoy, R., (1998), “A capacity allocation problem with integer side constraints,” European Journal of Operational Research, Vol. 109, No. 1, pp. 170-182.
    Wang, K. J., Wang, S. M, and Yang, S. J., (2007), “A resource portfolio model for equipment investment and allocation of semiconductor testing industry,” European Journal of Operational Research, Vol. 179, No. 2, pp. 390-403
    Wu, S. D., Erkoc, M., and Karabuk, S., (2005), “Managing Capacity in the High-Tech Industry: A Review of Literature,” The Engineering Economist, Vol. 50, No. 2, pp. 125-158.

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