對於現在或未來的快閃記憶體發展,多階技術已成為不可或缺的技術,而對於NOR型多階感測放大器的效能來說,感測速度及功率消耗是兩大影響指標,在本論文提出的多階感測放大器,使用兩級開迴路比較器及一顆參考細胞並運用自動調整參考感測電流來感測四個準位.這種架構比傳統電流感測方法有較少的功率消耗以及節省佈局面積,而感測速度也能達到一般NOR型快閃記憶體的高速運用,並且也比傳統電壓感測方法快.除此之外,此電路的感測解析度可低到20毫伏及2微安培的電流差異也增加多階快閃記憶體讀取的極限.
本論文的電路使用台積電0.18微米製程來實現,從下線晶片的量測結果顯示,此架構的多階感測放大器消耗功率只有1毫瓦,而感測速度最慢約為28奈秒.

The Multi-level technology has been essential for the modern or future flash memory. For NOR Flash memory, the sensing time and power consumption both dominate the performance of Multi-level sense amplifier. The approach of this thesis was designed to automatically adjust sensing current of reference cell to sense four levels and uses two stage open-loop comparator and one reference cell. This approach has less power consumption and less layout area than the current sensing of conventional method. Sensing time of this approach also achieves the target of NOR Flash memory for high speed application and is faster than the voltage sensing of conventional method. Besides, the sensing resolution can be lowered to 20mv and the minimum current difference is 2μA, which increases the read margin of Multi-level Flash memory.
The proposed Multi-level sense amplifier was realized in TSMC 0.18μm CMOS process and the experimental results show that the power consumption per sense amplifier is only 1mW and the worst sensing time is 28ns.

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