半導體製造流程是非常複雜的，而且需要昂貴的原料、精密的機器，也必須在高標準的製造環境中才能生產。半導體產業具有高成本、低生命週期的特性，所以如何提升製程的良率，以達到減少生產成本，已經成為一門重要的課題。如果我們可以在設計階段就找出可能發生問題的原因，也就是在問題還沒發生之前就將這些可能發生的問題找出並加以解決，不僅可以避免不必要的製造成本，還可以縮短產品上市的時間。因此，設計工程師在設計的階段找出影響良率的因子，並將這些因子考慮進去，對於改善良率會是一個好的方法。
晶圓表面電路密度的變異，會降低晶圓表面的平坦度，在化學機械研磨時，由於研磨墊加壓於晶圓表面上的應力分布不均 會造成表面凹陷的品質不良現象，稱之為碟盤效應 (Dish Effect)。為了解決此一問題，我們將晶圓表面上密度較低的區域填入虛擬電路 (Dummy Circuits)，以降低電路密度的變異，並可以同時消除碟盤效應。填入虛擬電路的目的，是要使晶圓表面的樣板密度較均勻，本研究透過一個有效的運算方法，探討虛擬電路的填充方法，以增加電路密度而改善晶圓表面的平坦度並且提升良率。此外，為了降低資料的複雜度，我們進行兩階段資料群集分析，以簡化龐大的資料分析過程。接著在不違反電路規則之下，使用數學規劃的方法求解虛擬電路的填充問題。
本研究使用某一半導體廠的電路資料，經過兩階段分群分析以及數學規劃求解出來的結果，使得整體電路密度提升，也成功的降低了密度的變異。

The process of semiconductor fabrication is very complex and it needs expensive materials, precise machines and high-standard environment for production. Semiconductor industry has the characteristics of high cost and low life cycle, so how to enhance yield such that the manufacturing cost can be reduced has become one of the most important issues. Finding out the factors which will affect yield and involving the production design engineer to consider these influence factors in the design phase is a good method to improve yield.
The purpose of the Chemical Mechanical Polishing (CMP) process is to planarize heights caused by the deposition of thin films over existing nonplanar features such that further levels may be added onto a flat surface. If there is no flat surface, it is unable to photolithography the line on the surface. Dish effect is due to the fact that the pad exerts different stresses upon the wafers. Because the variability of the circuit density, it will decrease the planarity of the wafer surface. Caves and defects may therefore be formed after the CMP process. To solve this problem, it is necessary to insert dummy circuits into low-density layout regions such that the variability of the circuit density can be reduced, the dish effect can hopefully be eliminated and yield can be increased at the same time.
The objective of dummy circuits is to make pattern density more uniform across a die. This research focuses on how to insert dummy circuits in original circuit layout to increase the circuit density, improve the planarity of the wafer surface, and therefore improve the yield. Through an efficient algorithm, it is possible to find out an appropriate method of inserting dummy circuits. And it can improve the variability of the circuit density and uniformize the stresses exerted upon the wafer in the process of CMP. It is expectable that the failure will be reduced in the process of CMP. Besides, we want to reduce the complexity of data analysis. So we use a circuit layout diagram as a Blue Print to perform a two-stage clustering analysis which can reduce the complexity of the data. And then we use Mathematical Optimization method to solve the optimizing dummy circuits problem under a current circuit design.
In this research, we use a circuits diagram provided by a semiconductor enterprise. Through a two-stage clustering analysis and mathematical optimization method, we insert dummy circuits into low-density layout regions. The results show that this method can successfully increase the density of the circuits and reduce the standard deviation of density.

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