在現今的CMOS製程裡, 八層甚至是更多的金屬連接層是很常見的情形. 於是將層的表面予以平坦化的技術已經變得相當重要. 化學機械研磨(CMP)是可以達到此一平坦化目的一項技術並且為了達到更好的平坦化效果和更高的可製造性. 我們一併使用了dummy metal填充這項技術來達到更佳的化學機械研磨效果. 在做實體電路布局時,此兩項技術都已經廣泛的被業界所採用. 隨著製程不斷不斷的縮小, 因為化學機械研磨這項技術所造成的金屬碟化效應(dishing)和金屬層侵蝕效應(erosion)使得dummy metal填充更顯重要. 但同時,dummy metal填充也造成了額外的寄生效應使得金屬連接線之間的電容因此變大. 所以dummy metal填充所造成的這些寄生效應是需要被準確的計算出來並且在設計電路的過程之中把這些效應考慮進去. 我們必須將dummy metal填充所造成的這些寄生效應加以量化. 而且也需要有更多針對這些效應的研究來幫助我們更了解這些寄生效應的問題.

在這篇論文裡, 首先我們會先概述dummy metal相關的知識. 接下來我們會針對一些已經發表過的相關文章作探討. 在分析過這些文章的優劣以後, 我們將會提出一個新的方法來量化dummy metal填充對電路所產生的寄生效應, 包含了電容, 效能及雜訊干擾…等等. 接著, 我們把我們的實驗所產生的數據加以分析並且得到了一些結論. 這個方法和這些結論能幫助設計電路的人預先並且正確的估計dummy metal填充對整個電路的影響. 最後我們同時設計了一個可以將這些量化的流程自動化執行的軟體. 藉由我們的軟體, 使用者可以針對他們個人的需求去設計他們所需要的測試結構 (例如:線長, 線寬, 線距, 哪一種製程…等等) 並且可以在最短的時間之內就可以得到因dummy metal填充所造成的這些寄生效應的大小.

In modern CMOS processes, eight or more interconnect layers are commonplace so that techniques to planarize the surface have become mandatory. Chemical-mechanical polishing (CMP) step is a technique to achieve planarization and dummy metal fills have been widely applied by foundries to VLSI physical layouts for better CMP uniformity and higher manufacturability. As the size getting smaller and smaller, dummy metal fills remain importantly because of dishing and erosion that are caused by CMP. But at the same time, dummy metal fills also cause extra parasitic effects which force the capacitance between interconnects becomes larger. Thus, the impact by dummy metal fills in circuit needs to be modeled accurately and be taken into account in the design flow. It is important to quantify these problems caused by dummy fills and need more researches for better understanding them.

In this paper, we will first overview the domain knowledge about dummy metal. Then we will review the related researches in this domain. After that, we’ll present a new and different method (structure) to quantify the impact by dummy metal fills in capacitance, on performance and crosstalk noise. We also analyze the experiment data from our method and make some conclusions. This can help designers to estimate the dummy impact accurately in advance. At last, we also design a software to run the flow automatically. With the software, users can generate the test structures according to their requests (for example: structure length, structure width, structure space and VLSI manufacturing processes) and quantify the parasitic impacts by dummy metal fills in a short time.

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