使用氮化矽做電荷儲存層之電荷陷阱式快閃記憶體，由於許多問題(如低介電係數及較大的band offset)而無法滿足元件微縮發展的趨勢，因此利用高介電係數材料取代氮化矽結構作為電荷儲存層之電荷陷阱式快閃記憶體元件是未來發展的趨勢。然而傳統以二氧化鉿作為儲存層的TAHOS元件結構，亦存在許多問題(如電荷陷阱較淺及較大的valence band offset)而無法滿足元件特性上的要求，因此便引進了堆疊式電荷儲存層結構以提升元件操作效能，但此時面臨到的是需要使用較大操作電壓以及耐力特性不佳的種種問題。
本實驗使用核研所浸潤式離子佈植機，以不同的氮摻雜時間及能量，氮化元件的高介電係數材料。研究主要是利用氮化後材料具有不同的特性，配合堆疊的結構，藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性，達成各項操作特性的提升。本論文研究的方向主要分為下列三步驟:
1.探討使用單層高介電材料作電荷儲存層，將其氮化後應用在電荷陷阱式快閃記憶體，討論其對元件特性研究。
2. 將氮化濃度拉高，並藉TAHNOS結構之電荷陷阱式記憶體，釐清氮化濃度、深度對元件各種操作特性的影響。由前項討論可發現氮化時間越長，越能提升元件特性，而除了將氮化時間拉至極限外，找出此條件下最佳氮化之濃度、深度是本項實驗所要做的。
3. 將前項結果應用於高介電係數、不同種類之堆疊式電荷儲存層記憶體元件，找出適合使用PIII最佳氮化濃度、時間之最佳堆疊式電荷儲存層結構。並且對其特性做討論。
由實驗結果可發現，引進PIII氮化技術應用於適當的堆疊式電荷儲存層，將有效提升各種操作特性，並且成功達成小電壓操作的目標。

[1] Harry Pon , et al. , “Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications” , International Conference on Solid-State and Integrated Circuit Technology , Oct. 2006 , page(s):697-700
[2] Min She, “semiconductor Flash Memory Scaling” , University of California, Berkeley , Doctor of Philosophy , 2003
[3] A. Paul, Ch. Sridhar, et al, “Comprehensive Simulation of Program, Erase and
Retention in Charge Trapping Flash Memories” International Device Electron Meeting , 2006 , page(s)1-4
[4]Y. N. Tan, et al. , ” Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer” IEEE Transactions on Electron Device Device,Vol.51 , No.7, 2004, page(s): 1143- 1147
[5]J. V. Houdt, et al. , ”High-k materials for nonvolatile memory applications”, International Reliability Physics Symposium , April 17-21,2005 , page(s):234-239
[6]T. Sugizaki, M. Kobayashi, et al. , “Novel Multi-bit SONOS Type Flash Memory using a High-k Charge Trapping Layer” , VLSI Technology Symposium , 2003 , page(s):27-18
[7]Y. N. Tan, et al., “High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation” , International Electron Device Meeting , 2004 , page(s):889-892
[8]M. S. Joo, et al., ”Dependence of Chemical Composition Ratio on Electrical
Properties of HfO2 Al2O3 Gate Dielectric” , Japanese Journal of Applied Physics. , No.3A, page(s):1220-1222 , March , 2003
[9]W.J. Zhu , et al. ”Effect of Al Inclusion in HfO2 on the physical and electrical properties of the dielectrics”, IEEE Electron Devices Letters,Vol.23,NO.11, Page(s):649-651,2002
[10]G. Molas et al. , “Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications” International Electron Device Meeting , 2007 , page(s):453-456
[11]Y. N. Tan , “Hafnium Aluminum Oxide as Charge Storage and Blocking-Oxide Layers in SONOS-type Nonvolatile Memory for High-Speed Operation” , IEEE Transactions on Electron Devices , April 2006 , Page(s):654-662
[12] Z. L. Huo et al. , “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory” , VLSI Technology Symposium , 2007 , page(s):138-139
[13] Tsunehiro INO et al. , “Dielectric Constant Behavior of Hf–O–N System” , Japanese Journal of Applied Physics , 2006, vol. 45, no. 4B, pp.2908-2913
[14] H. J. Yang et al. , “Comparison of MONOS Memory Device Integrity When Using Hf1−x−yNxOy Trapping Layers with Different N Compositions” , Transactions on Electron Devices , 2008, vol. 55, no. 6, pp.1417-1423
[15]J. Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage” , IEEE Aerospace Conference paper , P5-2383 5-2390, 2002
[16]M. H. White, et al. , “A low voltage SONOS nonvolatile semiconductor memory technology” , IEEE transactions on Components, Packaging, and Manufacturing Technology , June 1997 , page(s):190-195,
[17]W.J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell” , International Electron Device Meeting , 2001 , Page(s):32.6.1-32.6.4
[18]K. T. San , et al. , “Effects of erase source bias on Flash EPROM device reliability” , IEEE Transactions on Electron Devices, V January 1995 , page(s):150-159
[19]M. Chang et al. , “Charge loss behavior of a metal alumina nitride oxide silicon type flash memory cell with different levels of charge injection” , Applied Physics Letters , 2008 , page(s):232105-232105-3
[20]G. Verma, et al. , “Reliability Performance of ETOX Based Flash Memory” , International Reliability Physics Symposium , 1998 , page(s):158-166
[21]S. Haddad, et al. , “Degradation Due to Hole Trapping in Flash memory cells” , IEEE Electron Dev. Letters , 1989 , page(s):117-119
[22] Z. H. Ye et al. , “Enhanced Operation in Charge-Trapping Non-Volatile Memory Device with Si3N4/Al2O3/HfO2 Charge Trapping Layer,” IEEE Electron Device Letters, 2012, pp.1024-1028
[23]ITRS , Process Integration Devices and the structures , 2007 , pp. 35-37
[24] P.H. Tsai et al. , ” Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer ,” IEEE Electron Device Letters, March 2008, vol. 29, no. 3, pp.265-268
[25] G.D. Wilk, et al. , “High-K gate dielectrics: Current status and material properties considerations” , Journal of Applied Physic , 2001, page(s): 5243-5275
[26] C. J. Huang et al. , “Performance Enhancement of Silicon Nanowire Memory by Tunnel Oxynitride, Stacked Charge Trap Layer, and Mechanical Strain” , IEEE Electron Device Letters , 2012, vol. 33, no. 1, pp.20-22
[27] Y. Q. Wang et al. , ” Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack ,” Electron Devices Meeting, 2006, page(s): 1-4
[28] P. H. Tsai et al. , “Charge-Trapping-Type Flash Memory Device With Stacked High-k Charge-Trapping Layer,” IEEE Electron Device Letters, 2009, vol. 30, no. 7, pp.775-777
[29] Y. Q. Wang et al. , “Electrical Characteristics of Memory Devices With a High-k HfO2 Trapping Layer and Dual SiO2/Si3N4 Tunneling Layer” , Transactions on Electron Devices , 2007, vol. 54, no. 10, pp.2699-2705
[30] J. Buckley et al. , “In-depth Investigation of Hf-based High-k Dielectrics as storage layer of charge-trap NVMs,” in IEDM. Tech. Dig., 2006, pp.1-4