在本篇論文中，我們針對先進視訊影像壓縮技術 (H.264　Advanced Video Coding) 提出一個有效率的變動長度解碼反離散餘弦轉換和反量化架構設計。我們的設計支援省略模式功能在輸入區塊（Block 16x16 8x8 4x4）經由運算後的結果全為零值時，略過核心運算，直接輸出零值，由此減少運算的時間以及消耗的功率。而相較於傳統的設計，我們加入了變動長度解碼的功能，因此減少了記憶體存取需求。目前，我們已經將提出的架構設計整合入實驗室發展的H.264影像解碼器中，同時也在ＦＰＧＡ發展板上做驗證和實驗。

We propose an efficient hardware architecture for Inverse Quantization/Inverse Discrete Cosine Transform (IQ/IDCT) in H.264/AVC. Our design supports bypass mode for skipping blocks with zero transformed coefficients. We integrate Run Level Decoding (RLD) into our IQ/IDCT to reduce memory bandwidth. We have integrated the hardware IQ/IDCT into an H.264/AVC main profile decoder in FPGA prototype.

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[12] http://www.novas.com
[13] http://www.transeda.com
[14] http://www.synopsys.com
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