適用於張量壓縮式感測之多維區塊正交匹配追蹤處理器積體電路設計

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研究生：	王柔蓁 Wang, Jou-Chen
論文名稱：	適用於張量壓縮式感測之多維區塊正交匹配追蹤處理器積體電路設計 VLSI Design of N-way Block Orthogonal Matching Pursuit Processor for Tensor Compressive Sensing
指導教授：	黃元豪 Huang, Yuan-Hao
口試委員:	蔡佩芸 Tsai, Pei-Yun 陳喬恩 Chen, Chiao-En
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2021
畢業學年度：	110
語文別：	英文
論文頁數：	85
中文關鍵詞：	壓縮式感知、張量壓縮式感知、正交匹配追蹤、多維區塊正交匹配追蹤、超大型積體電路
外文關鍵詞：	Compressive sensing, Tensor compressive sensing, Orthogonal matching pursuit, N-way block Orthogonal matching pursuit, VLSI
相關次數：	點閱：3 下載：0
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壓縮感知已成為數位信號處理理論中的一項重要技術。壓縮感知可以通過較低的取樣率來對具有稀疏表示的信號進行取樣及重建，從而降低計算複雜度。但前提是信號必須是向量的形式。在這個前提下，如果壓縮感知要處理灰階圖像、RGB圖像、視頻等多維度的張量信號，必須先將信號做向量化，展成長向量，然後再用維度較大的感知矩陣進行測量。該方法計算複雜度高，使得傳統的壓縮感知理論不適用於張量信號。因此，張量壓縮感知通過利用沿著各維度產生的可分離式感知矩陣解決了上述問題，並有研究根據張量壓縮感知取樣後的信號，提出了兩個主要的重建演算法，廣義張量壓縮感知和多維區塊正交匹配追踪，而本文則提出了一種改進的多維區塊正交匹配追踪演算法。儘管多維區塊正交匹配追踪是一個成熟的重建演算法，但由於使用了丘列斯基分解及在重建過程中計算的數據之間有高度相依性，使它仍然難以用做硬體實現。而所提出的演算法在沒有任何效能損失的情況下，除了大幅降低原始多維區塊正交匹配追踪演算法的計算複雜度之外，同時提升計算的數據之間的獨立性，以利於硬體的平行化設計。最後，本研究基於改進的多維區塊正交匹配追踪演算法設計出多維區塊正交匹配追踪處理器的智慧財產權核生成器，並以型號為Zynq UltraScale+ MPSoC ZCU102 / xczu9eg-ffvb1156-2-e 的現場可程式邏輯閘陣列實現。

Compressive sensing (CS) has become a significant technique in the digital signal processing theory. The CS figures out that signals with a sparse representation can be reconstructed by a lower data rate which reduces the computational complexity. However, there is a premise that data must in the form of vectors. Under this premise, if the CS wants to deal with signals with multidimensional forms, such as gray images, RGB images and videos, the signals must be vectorized into long vectors first and then be measured by large sampling matrices. This method causes a high computational complexity and makes conventional CS theory not suitable for tensor signals. As a result, the tensor compressive sensing (TCS) tackles the above problems by utilizing separable sensing operators along tensor modes, and two main reconstruction algorithm were proposed, the generalized tensor compressive sensing (GTCS) and the N-way block orthogonal matching pursuit (N-BOMP). In this thesis, a modified N-BOMP algorithm is proposed. Although the N-BOMP is a well-developed reconstruction algorithm, it is still impractical because of the usage of the Cholesky decomposition and the high dependency of the data computed in the process of the reconstruction. The proposed algorithm makes a substantial reduction of the computational complexity of the original N-BOMP algorithm without any reconstruction performance loss. In addition, the proposed algorithm is also suitable for hardware design because its high data independency and an IP generator of the N-BOMP processor was designed. The proposed IP generator of the N-BOMP processor was implemented by field programmable gate array (FPGA) on device Zynq UltraScale+ MPSoC ZCU102 of xczu9eg-vb1156-2-e.

摘要
目錄
Introduction ------ 1
Background ------ 5
1 Basic Definition of Tensor ------ 5
1.1 Mode-n Tensor ------ 5
1.2 Mode-i Vector ------ 6
1.3 Mode-i Unfolding Matrix ------ 6
2 Multi-linear Algebra ------ 7
2.1 Mode-k Tensor by Matrix Product and Tucker Model ------ 7
2.2 Kronecker Product ------ 9
2.3 Schur-Banachiewicz Block-wise Matrix Inverse ------ 10
3 Compressive Sensing and Reconstruction Algorithms ------ 10
3.1 Compressive Sensing Model ------ 10
3.2 Orthogonal Matching Pursuit ------ 12
3.3 Matrix Inverse Bypassed Orthogonal Matching Pursuit ------ 13
4 Tensor Compressive Sensing ------ 17
4.1 Sparse Representation of Tensor Signals ------ 17
4.2 Tensor Compressive Sensing ------ 18
Proposed Modified N-way Block Orthogonal Matching Pursuit for
Tensor Compressive Sensing ------ 21
1 N-way Block Orthogonal Matching Pursuit ------ 21
2 The Proposed Modified N-way Block Orthogonal Matching Pursuit Algorithm ------ 24
Simulation Results and Performance Analysis ------ 43
1 Simulation Settings ------ 43
2 Computational Complexity Analysis ------ 46
3 Elapsed Time and Floating Point Operation Analysis ------ 47
4 Reconstruction Performance Analysis ------ 49
VLSI Design and Implementation Results ------ 57
1 Architecture Design ------ 57
1.1 Degree of Parallelism ------ 57
1.2 Hardware Design Algorithm 1 ------ 60
1.3 Hardware Design Algorithm 2 ------ 64
2 Circuit Design ------ 70
2.1 Initialization ------ 70
2.2 Index Selection Circuit ------ 71
2.3 Processing Element ------ 72
3 Timing Schedule ------ 73
4 Fixed-Point Simulation and FPGA Implementation Results ------ 74
4.1 Fixed-Point Simulation ------ 74
4.2 FPGA Implementation Results ------ 75
Conclusion and Future Works ------ 81
參考文獻 ------ 83
                                

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