我們使用有電極電鍍，以傳統濺鍍銅種子層的方法，配合不同的沉積條件，沉積銅膜在擴散障礙層鉭及氮化鉭上，研究其薄膜性質；並發展電化學的方法在矽上置換銅種子層，研究其薄膜性質後，配合有電極電鍍銅，與傳統沈積方法比較其熱穩定性與孔洞填充能力。
首先我們以傳統方法平面沉積有電極電鍍銅在不同擴散障礙層，控制沉積溫度、添加劑、電流密度、電鍍時間以及回火的處理，分別從四點探針、X光繞射分析儀、掃描式電子顯微鏡，觀察銅膜電阻率、結晶晶相、晶粒大小和薄膜的緻密度。其次我們以置換法沈積銅種子層，研究在不同置換時間、矽膜厚度及附著層，其電阻率、附著力、結晶晶相及晶粒大小。同時我們以鉭為附著層，鍍上一層多晶矽，再以置換法製備銅種子層，並沈積有電極電鍍銅為金屬層，製作電容構造，經過300。C至500。C，30分鐘的高溫處理，觀察電容電壓曲線的變化，並以歐傑電子質譜儀及二次離子質譜儀來配合驗証銅擴散的現象。另外我們也配合以不同方法製作的銅種子層，沉積有電極電鍍銅在0.35μm，aspect ratio~2.5的via群基板，以掃描式電子顯微鏡觀察對填充能力的影響。

由上述實驗分析結果，有電極電鍍沉積銅膜的電阻率可以達到1.86μΩ•cm，顆粒大小約為300A，主要晶相為Cu(111)；以傳統濺鍍銅種子層及矽上置換銅種子層配合有電極電鍍銅沈積在鉭及氮化鉭上，熱穩定性均可達到450。C，可配合ULSI後段製程；有電極電鍍銅沉積孔洞的填充能力可以填充0.35μm，aspect ratio~2.5的孔洞，而由於置換銅子層的技術，擁有良好的步階覆蓋能力，使孔洞底部仍有足夠厚的導電層，增進填充更小線寬孔洞的可能性，可配合dual-damascene結構在ULSI上的應用。

We deposited electroplating copper with conventional sputtered Cu seed-layer on the diffusion barrier Ta and TaN. With various deposition recipe, from XRD, SEM and resistivity, we studied the properties of electroplated Cu film. We also developed the displacement method of Cu seed-layer on Si film with electrochemical reaction, integrated the electrolplating Cu film to fabricate MOS capacitors. From C-V, Auger and SIMS, we studied the thermal stability of the multi-layer.
First, we deposited blanked electroplating copper on different diffusion barriers. At various deposition temperature and current density, we electroplated Cu films and measured the resistivity, crystal orientation, grain size of the film from four-point probe, XRD, and SEM. Secondly, we deposited Cu seed-layer with displacement reaction. With various reaction time, silicon film thickness and adhesion layer, we measured the resistivity, adhesion and grain size. Meanwhile, we fabricated the poly-silicon/Ta/SiO2/Si structure. After displacing Poly-Si with Cu seed-layer, we then deposited electroplating Cu film and made MOS capacitors. After sintering at 300。C to 500。C for 30 min, we studied the flat-band shift of the C-V (1MHz) curve and compared it to the MOS capacitors using conventional methods. We also observed the diffusion of Cu ions after sintering by Auger and SIMS depth profiles.

From above study, electroplated Cu film has the best resistivity of 1.86μΩ•cm, grain size of 300A, the preferred crystal orientation of Cu(111). With two different methods fabricated Cu seed-layers, electroplated Cu deposited on diffusion barrier, both had the thermal stability of 450。C, and shown the ability of filling 0.35μm vias with aspect ratio~2.5.

The technique of displacement method of Cu seed-layer has better step coverage than the conventional sputtered Cu seed-layers. The former method is cheaper than CVD Cu, we believe that the integration of new displaced Cu seed-layer and electroplated Cu film will have benefit to develop the future ULSI process.

[1] X.W. Lin, “Future interconnect technologies and copper metallization”, Solid State Technology, Oct. 1998, p.63
[2] S. Peter, “Tantalum, Copper and Damascene: The Future of Interconnects”, Semiconductor International, Jun. 1998, p.91
[3] Noguchi M, Asamaki T, “Contact hole filling by Cu reflow self sputtering”, Electrochemistry, Nov. 1999, p.1046
[4] Gang Bai, Chien Chiang, J. Neal Cox, Sychyi Fang, Donald S.Gardner, “Copper Interconnection Deposition Techniques and Intergration”, Symposium on VLSI Technology Digest of Technical Papers, 1996, P.48
[5] U.L. Liou, ”Basic Characteristics of Cu CVD and Passivation Study of Cu Films”, 國立交通大學電子工程學系碩士論文, ESECG, 1998, pt6:4
[6] V.M. Dubin, S.D. Yosi, “Selective and blanket electroless copper deposition for Ultra-large Scale Integration”, J. Electrochem. Soc., Vol. 144, No. 3, Mar. 1997, p.898
[7] Yuri Lantasov, Roger Palmans, Karen Maex, “New plating bath for electroless copper deposition on sputtered barrier layers”, Microelectronic Engineering, 50, 2000 , p.441
[8] R.D. Mikkola, Q.T. Jiang, B. Carpenter, “Copper Electroplating For Advanced Interconnect Technology”, Plating and surface finishing, Mar. 2000, p.81
[9] M.J. Shaw, “Study on selective deposition of Cu films on Si(100) substrates at ambient pressure”, 國立交通大學電子工程學系碩士論文, MSECG, 1998, pt1:2
[10] M. K. Lee, J.J. Wang, H. D. Wang, “Deposition of Copper Films on Silicon from Cupric Sulfate and Hydrofluoric Acid”, Journal of Electrochemical Society, May. 1997
[11] Allen C. Hamilton Jr., “Acid Sulfate and Pyrophosphate Copper Plating”, Plating and Surface Finishing, 1998, p.24
[12] T. Thomas, R. Thomas, “Electroplating bath control for copper interconnects”, Solid State Technology, Nov. 1998, p.47
[13] W.C.Gau, T.C.Chang, J.C. Hu, “Copper electroplating for future ultralarge scale integration interconnection”, Journal of Vacuum Society Technology A, vol. 18, No. 2, Mar/Apr. 2000
[14] L.A. Nagahara, “Effectfs of HF solution in the electroless deposition on silicon surfaces”, American Vacuum Society, Vol. 11, No. 4, Jul/Aug 1993, p. 763
[15] Sebastiao G. dos Santos Filho, “A mechanism for electroless Cu plating onto Si”, Microelectronic Engineering, Vol. 33, 1997, p.149
[16] M.K. Lee, H. D. Wang, “A Cu seed layer for Cu deposition on silicon”, Solid-State Electronics, Vol. 41, No. 5, 1997, p. 695
[17] DIETER K. SCHRODER, “Semiconductor Material and Device Characterization”
[18] 汪建民等, ”材料分析”
[19] 張俊彥等, “積體電路製程及設備技術手冊”
[20] H.C. Chen, M.S. Yang, “The Investigation of electroplating Deposited Copper Films for Advanced VLSI Interconnection”, IITC 99, IEEE, 1999, p. 65
[21] S. Lagrange, “Self-annealing characterization of electroplated copper films”, Microelectronic Engineering, vol.50, 2000, p. 449