為了持續改善MOSFET電晶體的性能，金氧半元件的尺寸被要求越來越小，在未來CMOS技術中等效氧化層厚度(EOT)甚至被要求縮小到1nm以下。然而當二氧化矽縮小到1.5nm以下時，閘極漏電流變得相當顯著且無法接受。High-k介電層已被廣泛應用來解決這個問題，因為較厚的介電層可以降低電子或電洞穿隧閘極介電層的可能性，進而減少漏電流。但是High-k材料仍然面臨一些技術性的挑戰，例如charge trapping和遷移率惡化...等問題。
為了解決這些問題而引伸出界面處理以及改變通道材料以提升載子遷移率...等方法。純鍺相對於矽而言，載子遷移率分別對電子提升了兩倍以及對電洞提升了四倍之多，對於元件的驅動電流可獲得大大得改善，因此鍺成為改善通道材料的首選之一。但是由於鍺的熱穩定性不佳，在400℃下會產生易揮發的氣體且容易水解，這種情況會降低元件的電特性，所以勢必要用其他鈍化方式來抑制鍺的擴散並且維持鍺通道元件的電特性。
首先實驗上我們使用了超高真空化學分子磊晶系統(ANALVA SRE-612 UHVCME)於矽基板上磊晶矽鍺(Si0.8Ge0.2)25nm形成虛擬基板以達成矽鍺通道MOSFET元件，接著在矽鍺上磊晶不同厚度(15nm~25nm)的矽覆蓋層，藉此探討不同矽覆蓋層厚度對元件的電特性影響。但是由於此矽覆蓋層厚度加上介電層厚度20nm在後續的S/D活化900℃, 30秒下無法有效阻擋鍺擴散，使得元件漏電流異常得大且無field effect。
為了改善上述問題，之後實驗樣品的S/D活化溫度均改為600℃、時間30分鐘。
第一部分我們依然探討磊晶不同矽覆蓋厚度對元件得電特性影響。實驗結果顯示，在使用35nm矽覆蓋層厚度的元件不管電特性或可靠度皆有較好的表現，顯示35nm矽覆蓋層在600℃下可有效阻擋鍺的擴散。
第二部分我們為了進一步提升元件電特性，針對由ALD成長的HfAlO/HfO2介電層施以電漿浸潤式離子佈植(PIII)的方式，由閘極上方摻雜N至介電層中，藉此探討不同氮化能量對元件電特性的影響。由實驗結果顯示，經過氮化處理的元件在電特性和可靠度上均得到提升，而氮化能量在5kev的元件則因佈植能量太高導致通道破壞，使得電特性表現下滑。

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