具自適應式電容切換技術之低功耗非同步漸近式類比數位轉換器之設計與製作

簡易檢索 / 詳目顯示

回結果列表

研究生：	黃信元 Huang, Hsin-Yuan
論文名稱：	具自適應式電容切換技術之低功耗非同步漸近式類比數位轉換器之設計與製作 The Design and Implementation of Power-Efficient Asynchronous SAR ADC with Adaptive Digital-to-Analog Converter Switching Technique
指導教授：	謝志成 Hsieh, Chin-Cheng
口試委員:	謝志成 Hsieh, Chin-Cheng 盧志文 Lu, Chih-Wen 陳巍仁 Chen, Wei-Zen 洪浩喬 Hong, Hao-Chiao
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	84
中文關鍵詞：	連續漸進式類比至數位轉換器 Successive
外文關鍵詞：	Successive Approximation analog-to-
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文描述了兩個應用低功耗生醫電路之超低功耗10位元非同步漸近式類比數位轉換器（SAR ADC) 的設計。所提出的兩個類比數位轉換器之供給電源為0.7V至1V，採樣頻率則為250kS/s至1MS/s。所提出的非同步漸近式類比數位轉換器利用多種技巧來提高ADC功率效率。首先提出一個以分裂式電容切換方式為基礎的自適應式電容切換技術（adaptive digital-to-analog converter switching, ADS），以減少平均切換電容數和來提高電容切換效率。也利用高度匹配的金屬類型單位電容來降低單位電容值進一步減少電容切換功耗。最後，利用動態SAR控制器來減少電晶體數目進一步的優化數位和類比電路之間的功耗權衡。
為驗證本電路，本論文利用0.18微米混合式訊號CMOS製程來實現此二顆實驗晶片。第一個實驗晶片操作在1V供給電源和500kS/ s的採樣率。在接近Nyquist頻率所測得的有效位元數（ENOB），是9.24位元。總功耗為14.2微瓦，等效的figure of merit（FoM）則為47fJ/Conversion-step。
第二個實驗晶片則是第一顆實驗晶片的優化版本。操作電源從0.7V到0.9V。在操作電源和取樣頻率為0.9V和1MS / s時的ENOB和總功耗分別為9.33位元和7.84微瓦。由此產生的FoM則是12.1fJ/conversion-step。當操作電源和取樣頻率為降低至0.7V和250KS/ s時的總功耗只有1.07微瓦。由此產生的ENOB和FOM在接近Nyquist的輸入頻率分別是8.8位元和9.58fJ/conversion-step。

Chapter 1  Inroduction    11
1     Architecture Selection    12
2     Performance Metrics of SAR ADCs    14
2.1     Resolution    14
2.2     Quantization Noise    14
2.3     Differential Nonlinearity (DNL) and  Integral Nonlinearity (INL)    15
2.4     Signal-to-Noise Ratio (SNR)    15
2.5     Effective Resolution    16
2.6     Figure of Merit (FoM)    16
3     Motivation    16
4     Target Specifications    17
5     Thesis Organizations    18
Chapter 2    Successive Approximation Register    (SAR ) ADC Overview    19
1     Global Operation of SAR ADC    19
1.1     Sources of Error    20
2     Sampling Network    22
2.1     On-Resistance of MOS Switch    22
2.2     Charge Injection and Clock Feedthrough    24
2.3     Thermal Noise    25
3     Digital-to-Analog Converter    26
3.1     Binary Weighted DAC    26
3.2     DAC Parasitic Capacitance and Capacitor Mismatch    27
4     Device Mismatch of Comparator    28
5     Successive Approximation Register    29
6     Summary    30
Chapter 3     Circuit Design Considerations    31
1     Differential SAR ADC    31
2     CDAC Switching Energy    33
2.1     Energy Saving CDAC Switching in [7]    35
2.2     Monotonic Switching Procedure in [18]    38
2.3     Concepts of Adaptive DAC switching    40
3     Sample and Hold Design Consideration    41
4     Comparator Design Consideration    42
5     SAR Control Design Consideration    42
6     Summary    43
Chapter 4     Circuit Design    44
1     Capacitive DAC Design    44
1.1     Adaptive DAC Switching Operation    46
2     Sampling Network Design    50
3     Comparator Design    51
4     Asynchronous SAR Logic and DAC Control Logic Design    53
5     Enhancements of Prototype 1    56
6     Summary    58
Chapter 5     Measurements Results    59
1     Measurement Environment Setup    59
2     Measurements of First Prototype    60
2.1     Static Performance    61
2.2     Dynamic Performance    62
2.3     Performance Summary and Comparison    64
3     Measurement results of Second Prototype    65
3.1     Static Performance    67
3.2     Dynamic Performance    68
3.3     Performance Summary and Comparison    73
4     Summary    74
Chapter 6     Conclusion and Future work    76
1     Conclusion    76
2     Future Work    76
2.1     Comparator with Offset Compensation  and Supply Boost    77
2.2     Sampling Network Improvement    78
Bibliography    80

                                

[1] A. P. Chandrakasan, N. Verma, and D. C. Daly, “Ultralow-power electronics for biomedical applications, ” Ann. Rev. Biomed. Eng., vol. 10, no. 1, pp. 247-274, 2008.
[2] B. Murmann, “ADC Performance Survey 1997-2011, ” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
[3] H.-C. Hong and G.-M. Lee, “A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007.
[4] N. Verma and A. P. Chandrakasan, “A 25□w 100KS/s 12b ADC for wireless micro-sensor applications,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp.222-223.
[5] A. Anges, E. Bonizzoni, P. Malcovati, and F. Maloberti, “A 9.4-ENOB 1V 3.8□W 100KS/s SAR ADC with time-domain comparator,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp.246-247.
[6] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications, ”, in IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers, Nov. 2008, pp. 228-231.
[7] W.-Y. Pang, C-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, "A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications," in IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers, Nov. 2009, pp. 149-152.
[8] C.-H. Kuo and C.-E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique, ” in Proceedings of the ESSCIRC , Sept. 2011, pp.475-478, 12-16.
[9] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices,” in Proceedings of the ESSCIRC , Sept. 2011, pp. 467-470.
[10] S.-I. Chang, K. A.-Ashmouny, and E. Yoon, “A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application,” in Proceedings of the ESSCIRC , Sept. 2011, pp. 339-342.
[11] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M. Klumperink , and B. Nauta “A 10-bit Charge-Redistribution ADC Consuming 1.9□W at 1MS/s,” IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May. 2010.
[12] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, "A 0.5V 1.1MS/s 6.3fJ/Conversion-step SAR ADC with Tri-Level Comparator in40nm CMOS," in VLSI Symp. Tech. Dig., Jun.2011, pp.262-263.
[13] M. Yip and A. P. Chandrakasan, “A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011. pp. 190-192.
[14] P. Harpe, C. Chou, X. Wang, G. Dolmans, and H. de Groot, “A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS,” in Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp.388-389.
[15] B. P. Cinsburg and A. P. Chandrakasan, “An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC, ” in IEEE Int. Symposium on Circuits and Systems vol.1, May 2005, pp. 184-187.
[16] B. P. Ginsburg and A. P. Chandrakasan , “500-MS/s 5-bit ADC in 65-nm CMOS with Split Capacitor Array,” IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
[17] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.
[18] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-S. Lin, “A 0.92mW 50-MS/s SAR ADC in 0.13□m CMOS Process,” in VLSI Symp. Tech. Dig., Jun.2009, pp.236-237.
[19] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-S. Lin, “A 10-bit 50-MS/s SAR ADC With Monotonic Capacitor Switching Procedure,” IEEE Journal of Solid-State Circuits,.,vol. 45, no.4, pp.731-740, Apr. 2010.
[20] S.-K. Lee, S.-J. Park, H.-J. Park, and J.-Y. Sim, “A 21 fJ/Conversion-Step 100KS/s 10 bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface,” IEEE Journal of Solid-State Circuits,.,vol. 46, no.3, pp.651-659, Apr. 2011.
[21] J. H. Cheong, K. L. Chan, P. B. Khannur, K. Tee, and M. Je, " A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18um CMOS," IEEE Trans. Citcuit and Systems II. Exp. Briefs vol.58, no.7, pp 407-411, Jul., 2011.
[22] D. A. Johns, and K. Martin, Analog Integrated Circuit Design. John Wiley & Sons, In, 1997.
[23] B. Razavi, Data Converiosn System Design. IEEE Press, 1995.
[24] J. McCreary, and P. Gray, “All-MOS Charge-Redistribution Analog-to-Digital Conversion Techniques I, ” IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
[25] S. O'Driscoll, K. V.Shenoy, and T. H. Meng, “Adaptive Resolution ADC Array for an Implantable Neural Sensor, ” IEEE Trans. Biomed. Circuit Syst. vol.5, no.2, pp.120-130, April 2011.
[26] B. Razavi, Design of Analog CMOS Integrated Circuits. 1st ed. New York, NY: Mcgraw-Hill, 2001.
[27] A. Rossi, G. Fucili, “Nonredundant successive approximation register for A/D converters,” Electronics Letters, Vol.32, no.12, pp.1055-1057, Jun. 1996.
[28] R. K .Hester, K.-S. Tanm M. D. Wit, J. W. Fattaruso, S. Kiriaki, and J. R. Hellums, “Fully Differentail ADC with rail-to-rail common-mode range and non-linear capacitor compensation, ” IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 173-183, Feb. 1990.
[29] Y. S. Yee, L. M. Terman, L. G. Heller, “A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion,” IEEE Journal of Solid-State Circuits, Vol.14, no.4, pp.778-781, Aug. 1979.
[30] S.-K Lee, S-J Park, Y. Suh, H.-J. Park, and J.-Y. Sim,“ A 1.3□W 0.6V 8.7-ENOB successive approximation ADC in 0.18um CMOS, ” in VLSI Symp. Tech. Dig., Jun.2009,pp.242-243.
[31] Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, S.-P. U, and R. P. Martins, “A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs, ” in IEEE Int. Symposium on Circuits and Systems, May 2010, pp.4061-4064.
[32] Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M.Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda, “Split capacitor DAC mismatch calibration in successive approximation ADC, ” in IEEE Custom Integrated Circuits Conference, Sept. 2009, pp. 279-282.
[33] P.J.A. Harpe, C. Chou, Y. Bi, N. P. van der Meijs, X. Wang, K. Philips, G. Dolmans, and H. de Groot, “A 26w 8 bit 10MS/S Asynchronous SAR ADC for Low Energy Radios,” IEEE Journal of Solid-State Circuits, vol. 46, NO. 7, pp. 1-11, Jul. 2011.
[34] P. Harpe, C. Chou, X. Wang, G. Dolmans, and H. de Groot, “A 12fJ/Conversion-Step 8bit 10MS/S Asynchronous SAR ADC for Low Energy Radios,” in Proceedings of the ESSCIRC, , Sept. 2010, pp. 214-217.
[35] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, and C.-M. Huang, “ A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18□m CMOS,” in VLSI Symp. Tech. Dig., Jun.2010,pp.241-242.
[36] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999.
[37] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10-b 50-MS/s 820-□W SAR ADC With On-Chip Digital Calibration, ” IEEE Trans. Biomed. Circuit Syst. vol.4, no.6, pp.410-416, April 2010.
[38] R. Sekimiti, A. Shikata, Tadahiro, and H.Ishikuro, “A 40-nm 50S/s-8MS/s Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator,” in Proceedings of the ESSCIRC , Sept. 2011, pp. 471-474.
[39] S. U. Ay, “A CMOS Energy Harvesting and Imaging (EHI) Active Pixel Sensor (APS) Imager for Retinal Prosthesis, ” IEEE Trans. Biomed. Circuit Syst. vol.5, no.6, pp.535-545, Dec. 2011.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文