應用於高速傳輸之20對1多工器設計｜國立清華大學博碩士論文庫

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研究生：	蕭振祥 Chen-Hsiang Hsiao
論文名稱：	應用於高速傳輸之20對1多工器設計 A 3.2 Gbps 20 to 1 Source-coupled Logic Multiplexer of High-Speed Interconnect in 0.18um Technology
指導教授：	許雅三 Yarsun Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	55
中文關鍵詞：	多工器、高速傳輸
外文關鍵詞：	multiplexer
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由於近年來多使用八位元/十位元的編碼方式，所以大部分的傳輸介面都會採用一對八或一對十的解多工器。然而，當我們把此傳輸介面和其他高速的路由器或交換機整合在一起時，用一對十的解多工方式會使得交換機必須操作在320 MHz 的時脈下。所以，我們提出了一個1對20的傳輸介面，這樣就可以讓交換機或路由器的操作頻率降低到160 MHz。
在此篇論文中，主要是要介紹多工器的設計。因為速度上的要求，目前大部分的多工器都是採用BiCMOS,GaAs,silicon bipolar等製程去實現。但是因為價格以及系統整合的考量，在這裡我們使用CMOS製程去實現。而大部分我們看到的多工器都是採用樹狀的結構去實現，但這樣只能實現二的冪次方的多工器。在本論文中採用了位移暫存器結構，分別由兩排正緣觸發和負緣觸發的D型正反器以及多個2對1的多工器所組成。透過這個結構可以實現任意偶數位元的多工器設計，也由於速度上的考量，我們採用了SCL（Source-coupled Logic） circuits去實現這個架構。由於採用了這兩種方式，所以這個多工器兼具了高速以及高度的可擴充性。在論文的後半段也介紹了這個架構和其他部分整合時所會遇到的問題以及解決的方法。全部的設計都是建立在台積電TSMC 018μm CMOS 製程，設計結果顯示此20對1的多工器速度可以達到6 Gbps，以及20 picoseconds的抖動。

Almost all the transceivers adopt the 1:8 or 1:10 demultiplexing schemes due to the use of 8/10B CODEC. When integrating the transceiver with other high speed router or switch modules in a single chip, the 1:10 demultiplexing requires 320 MHz clock frequency to maintain the high data throughput rate. Therefore, we proposed a 1:20 transceiver IP that can reduce the operating frequency required in routers or switches by half.
Most of the multiplexers are implemented with BiCMOS, silicon bipolar, GaAs, SiGe, etc. Though these technologies have advantages of speed over CMOS, many researchers try to make optical communication component using CMOS, due to its inherent advantages of price, power and compatibility. And they often adopt the tree-type structure for it is relatively easier to get faster speed than other structure and that is the most direct way to fulfill the function of SONET. But it can only serialize the parallel data with the bit number of 2’s power. In this thesis, we use the double edge triggered shift register structure. Through this structure, an any even number of N to 1 multiplexer can be realized easily. And we adopt the SCL circuits to raise the operation speed of the multiplexer. However, our multiplexer has both the features of high speed and high flexibility.
This work has been implemented in a 0.18μm CMOS technology. The presented multiplexer design can achieve 6 Gbps data rate with 20:1 multiplexing and 20 picoseconds peak to peak jitter.

Content


List of Figures                                                         v
List of Tables                                                        viii
  Introduction                                                       1
1    Evolution of Multiplexer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   1
2    Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   3
3    Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
4    Organization of this thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
  Load-Balanced TDM Switch and SERDES Interface                     6
1    Two-stage Load-balanced Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
2    The 8×8 symmetric TDM Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
3    The CML Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
  20:1 Multiplexer Architecture                                        12
1    Introduction of the Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   12
2    20:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   13
3    2:1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   14
4    D-latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .    16
5    SEL Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
  Design and Simulation                                              20
1    Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   20
2    SCL circuit design and simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   21
2.1  SCL circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
2.2  SCL circuit simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
3  20:1 Multiplexer Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
        4.3.1  Pre-layout simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
        4.3.2  Layout of the 20:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
        4.3.3  Post-layout simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
        4.3.4  Select scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
4  Design of SEL signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  37
5  Comparison of Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
Integration                                                        41
1  Introduction of the transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
2  Integration of the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
        5.2.1  Integration of multiplexer and CML output buffer . . . . . . . . . . . . .  43
        5.2.2  PLL and SEL signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
3  Integration of the transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
4  Comparison of the transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
Conclusion and future work                                         52
Bibliography                                                         54




List of Figures


1    Multi-stage multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2
2    Single-stage multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3

1    The load-balanced Birkhoff-von Neumann switch with one stage buffering. . .  7
2    The folded version two-stage load-balanced switch. . . . . . . . . . . . . . . . . . . . . .  8
3    The 8×8 switch fabric architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4    The CML transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10

1    a  General differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
b  SCL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
2   20:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
3   2:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
4   D-latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
5   D flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
6   SEL signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
7   Digital 2:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   18
8   Digital D flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19

1    Full custom design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
2    One side of the SCL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
3    Pre-layout Simulation of the SCL D flip-flop at 1.6 GHz . . . . . . . . . . . . . . . .  24
4    Pre-layout Simulation of the SCL 2:1 multiplexer at 1.6 GHz . . . . . . . . . . . .  25
5    Single to differential converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6    Pre-layout simulation of the 20:1 Multiplexer at 1.6 GHz (tt) . . . . . . . . . . . . . 27
7    Pre-layout simulation of the 20:1 multiplexer at 1.6 GHz (ss) . . . . . . . . . . . . . 28
8    Simulation of the 20:1 multiplexer at 3 GHz (tt) . . . . . . . . . . . . . . . . . . . . . . . .29
9    Eye diagram of the 20:1 multiplexer at 1.6 GHz (tt) . . . . . . . . . . . . . . . . . . . . .30
10    Layout of a D flip-flop and a 2:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11    Layout of the 20:1 multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12    Post-layout simulation of 20:1 multiplexer at 1.6 GHz (tt) . . . . . . . . . . . . . . . . 33
13    Post-layout simulation of 20:1 multiplexer at 3 GHz (tt) . . . . . . . . . . . . . . . . . .33
14    Eye diagram of the post-layout simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
15    The last stage 2:1 multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
16    Output of the scheme1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
17    Output of the scheme2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
18    Output of the scheme3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
19    Single to differential converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
20    Layout of the SEL signal generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
21    Simulation if the SEL signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

1    3.2 Gbps 1:20 CML transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2    20:1 transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
3    CML output buffer and 20:1 multiplexer simulation . . . . . . . . . . . . . . . . . . . .  43
4    Eye diagram of the CML output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  43
5    Transmitter with clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   45
6    Block diagram of the clock tree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   45
7    Voltage swing conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   46
8    A cell of the multiplexer and setup time violation. . . . . . . . . . . . . . . . . . . . . .  47
9    Transmitter with retiming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
10    Synchronous and stable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  48
11    Waveform of the transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12    Eye diagram of the transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13    Eye diagram of the transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
14    Waveform of the transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50













List of Tables


Table 4.1  Comparison of Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 5.1  Comparison of Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

                                

Bibliography

[1] C. S. Chang, D. S. Lee and Y. S. Jou, “Load balanced Birkhoff-von Neumann switches, part I: one-stage buffering,” Computer Communications, Vol. 25, pp. 611-622, 2002

[2] C. S. Chang, D. S. Lee and C. M. Lien, “Load balanced Birkhoff-von Neumann switch, part II: Multi-stage buffering,” Computer Communications, Vol. 25, 2002, pp. 623-634

[3] C. S. Chang, D. S. Lee, and C. Y. Yue, “Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches,” Proceedings of IEEE INFOCOM, 2003.

[4] C. S. Chang, D. S. Lee and Y. J. Shih, “Mailbox switch: a scalable two-stage switch architecture for conflict resolution of ordered packets,” preprint, 2004.

[5] Y. Guo, Z. Zhang, W. Hu, L. YANG, “CMOS MULTIPLEXER AND DEMULTIPLEXER FOR GIGABIT ETHERNET”, Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on Volume 1, 29 June-1 July 2002 Page(s):819 - 823 vol.1

[6] Lu Jianhua, Tian Lei, Chen Haitao, Xie Tinging, Chen Zhiheng, Wang Zhigong, “Design Techniques of CMOS SCL circuits for Gb/s Applications”, ASIC, 2001. Proceedings 4thInternational Conference on 23-25 Oct. 2001 Page(s):559 – 562

[7] Ming-Dou Ker, Kai-Lan Chuang, ”Unify Output Buffers for Both LVDS and RSDS Standards”

[8] Nakura, T.; Ueda, K.; Kubo, K.; Matsuda, Y.; Mashiko, K.; Yoshihara, T,” A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology,” Solid-State Circuits, IEEE Journal of Volume 35, Issue 5, May 2000 Page(s):751 – 756

[9] A.L. Coban, M.H. Koroglu, K.A. Ahmed, ”A 2.5-3.125Gb/s Quad Transceiver with Second Order Analog DLL Based CDRs”, Custom Integrated Circuits Conference, 2004.

[10] Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, C.S.G. Conroy, Beomsup Kim, “A Four-Channel 3.125Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer”, Solid-State Circuits, IEEE Journal of Volume 40, Issue 2, Feb. 2005

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