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研究生: 何宜倫
Ho, Yi-Lun
論文名稱: 針對三維多核處理器效能優化之一種以溫度為考量的任務分配方法
A Thermal-Driven Task Allocation for 3D MCP Throughput Optimization
指導教授: 張世杰
Chang, Shih-Chieh
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 35
中文關鍵詞: 三維晶片效率優化任務分配
外文關鍵詞: 3D Multi-Core Processor, Throughput optimization, Task allocation
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  • 三維晶片已經變成一個新興的技術,由於它可以提高封裝密度以及相當大的異質整合彈性。然而在三維晶片中有著不易散熱的問題,使得在考慮優化三維多核處理器效能時,需要把高溫的影響考慮進來。此外在三維多何處理器裡,溫度受任務位置分配的影響很大,一個好的任務分配可以減少許多溫度帶來的問題以及增加效能。另外在這篇論文中,為了達到連線排程,我們提出了一個非常高效率的任務分配演算法可以在溫度限制下優化三維多核處理器效能。實驗結果顯示我們快速的演算法可以使128的多核處理器下的任務分配,在1微秒內完成。並且與LINGO軟體結果比較,我們的方法平均只差0.85%的效能。


    Three-dimensional integrated circuits (3D ICs) have become an emerging technology because of advantages of higher packaging density and more flexible in heterogeneous integration. However, due to the heat dissipation problem in 3D ICs, thermal issues must be considered when maximizing the throughput of 3D Multi-Core Processors (MCPs). Furthermore, since the thermal behavior of a core in 3D MCPs strongly depends on its location, a proper task allocation can reduce potential thermal problems and improve the throughput. In this thesis, to enable the possibility of on-line scheduling, we present a very high performance task allocation algorithm to solve the problem of throughput optimization under thermal constraints for 3D MCPs. The experimental results show our fast algorithm can finish in less than 1ms for 128 cores. Compared to solutions obtained from LINGO, our algorithm only has 0.85% throughput loss on average.

    Abstract i List of Contents: ii List of Figures: iii List of Tables: iv Chapter 1 Introduction 1 Chapter 2 Thermal, Power and Performance Model 6 2.1. Thermal Model 7 2.2. Power Model 9 2.3. Performance Model 11 Chapter 3 Problem Formulation 12 Chapter 4 Effective Task Allocation Algorithm 14 4.1. Basic Idea 15 4.2. Incremental Updates of Thermal Simulation 17 4.3. Task Allocation 19 4.4 Illustrative Example 20 4.5. Overall Algorithm and Complexity Analysis 24 Chapter 5 Experimental Results 26 Chapter 6 Conclusions 33 Reference 34

    [1]A. K. Coskun, T. S. Rosing, J. Ayala, D. Atienza, and Y. Leblebici. “Dynamic thermal management in 3D multicore architectures,” in Design Automation and Test in Europe (DATE), pp. 1410–1415, 2009.
    [2]V. Hanumaiah, R. Rao, S. Vrudhula and K. S. Chatha, “Throughput Optimal Task Allocation under Thermal Constraints for Multi-core Processors,” in Proc. of DAC, pp. 776-781, 2009
    [3]W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan and K. Skadron, “An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations,” in Proceedings of the Workshop on Duplicating, Deconstructing, and Debunking, in conjunction with the 34th International Symposium on Computer Architecture (ISCA), June 2007.
    [4]W. Huang, K. Skadron, S. Gurumurthi, R. J. Ribando, and M. R. Stan, “Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design,” in Proceedings of the 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Apr. 2009.
    [5]M. Kadin and S. Reda, “Frequency and Voltage Planning for Multi-Core Processors Under Thermal Constraints,” in IEEE International Conference on Computer Design, pp. 463-470, 2008.
    [6]Al Krum. Thermal management. In Frank Kreith, editor, “The CRC handbook of thermal engineering, “ pages 2.1–2.92. CRC Press, Boca Raton, FL, 2000.
    [7]W. Liao, L. He, and K. Lepak, “Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture Level,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24(7), pp. 1042--1053, 2005.
    [8]R. Rao and S. Vrudhula. “Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors,” in Proc. of ICCAD, pp. 537-542, 2008.
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    [10]C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, “Three-dimensional chip-multiprocessor run-time thermal management,” IEEE Transactions on CAD, 27(8):1479–1492, August 2008.

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